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1. 发明授权

US09368490B2 Enhancement-depletion mode inverter with two transistor architectures 有权
标题翻译：具有两个晶体管架构的增强耗尽型逆变器
公开(公告)号：US09368490B2
公开(公告)日：2016-06-14
申请号：US14526634
申请日：2014-10-29
申请人： Carolyn Rae Ellinger , Shelby Forrester Nelson
发明人： Carolyn Rae Ellinger , Shelby Forrester Nelson
IPC分类号： H01L27/088 , H01L29/786
CPC分类号： H01L27/0883 , H01L27/1225 , H01L27/1251 , H01L29/7869
摘要： An enhancement-depletion-mode inverter includes a load transistor and a drive transistor. The load transistor has a top gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The load transistor is configured to operate in a depletion mode. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness that is different from the load dielectric thickness. The drive transistor is configured to operate in a normal mode or an enhancement mode. The first source is electrically connected to the second drain and the first gate.
摘要翻译：增强耗尽型逆变器包括负载晶体管和驱动晶体管。负载晶体管具有顶栅结构，其具有第一源极，第一漏极，负载沟道区域，第一半导体层和第一栅极电极。负载栅极电介质位于负载沟道区域中，并具有负载介质厚度。负载晶体管被配置为在耗尽模式下工作。驱动晶体管具有底栅结构，其具有第二源极，第二漏极，驱动沟道区，第二半导体层和第二栅电极。驱动栅极电介质位于驱动沟道区域中，并且具有不同于负载介质厚度的驱动电介质厚度。驱动晶体管被配置为在正常模式或增强模式下操作。第一源电连接到第二漏极和第一栅极。

2. 发明授权

US09337828B2 Transistor including reentrant profile 有权
标题翻译：晶体管包括可重入型材
公开(公告)号：US09337828B2
公开(公告)日：2016-05-10
申请号：US14289678
申请日：2014-05-29
申请人： Lee William Tutt , Shelby Forrester Nelson
发明人： Lee William Tutt , Shelby Forrester Nelson
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8242 , H01L21/8224 , H03K17/687 , H01L29/66 , H01L29/786
CPC分类号： H03K17/687 , H01L29/66787 , H01L29/78642 , H01L29/78681 , H01L29/7869
摘要： A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile.
摘要翻译：晶体管包括衬底，导电材料层和电绝缘材料层。衬底，导电材料层和电绝缘材料层中的一个或多个的至少一部分限定了折入轮廓。

3. 发明授权

US09299853B1 Bottom gate TFT with multilayer passivation 有权
标题翻译：底栅TFT多层钝化
公开(公告)号：US09299853B1
公开(公告)日：2016-03-29
申请号：US14487161
申请日：2014-09-16
申请人： Carolyn Rae Ellinger , Shelby Forrester Nelson
发明人： Carolyn Rae Ellinger , Shelby Forrester Nelson
IPC分类号： H01L29/12 , H01L29/786
CPC分类号： H01L29/78696 , H01L29/7869
摘要： A transistor includes a gate in contact with a substrate. A gate insulating layer is in contact with at least the gate. An inorganic semiconductor layer is in contact with the gate insulating layer. There is a source electrode in contact with a first portion of the inorganic semiconductor layer and a drain electrode in contact with a second portion of the inorganic semiconductor layer, and the source electrode and the drain electrode are separated by a gap. There is a multilayer insulating structure in contact with at least the inorganic semiconductor layer in the gap. The multilayer structure includes an inorganic dielectric layer having a first pattern defining a first area; and a polymer structure having a second pattern defining a second area. The second area is located within the first area and the polymer structure is in contact with the semiconductor layer in the gap.
摘要翻译：晶体管包括与衬底接触的栅极。栅极绝缘层至少与栅极接触。无机半导体层与栅极绝缘层接触。存在与无机半导体层的第一部分接触的源电极和与无机半导体层的第二部分接触的漏电极，并且源电极和漏电极被间隙分开。存在与间隙中的至少无机半导体层接触的多层绝缘结构。多层结构包括具有限定第一区域的第一图案的无机介电层; 以及具有限定第二区域的第二图案的聚合物结构。第二区域位于第一区域内，聚合物结构与间隙中的半导体层接触。

4. 发明申请

US20150255624A1 VTFT INCLUDING OVERLAPPING ELECTRODES 有权
标题翻译： VTFT包括重叠电极
公开(公告)号：US20150255624A1
公开(公告)日：2015-09-10
申请号：US14198643
申请日：2014-03-06
申请人： Shelby Forrester Nelson , Carolyn Rae Ellinger , Lee William Tutt
发明人： Shelby Forrester Nelson , Carolyn Rae Ellinger , Lee William Tutt
IPC分类号： H01L29/786 , H01L29/10 , H01L29/423
CPC分类号： H01L29/78642 , H01L29/1037 , H01L29/42384 , H01L29/7869
摘要： A vertical transistor includes a substrate and an electrically conductive gate structure having a top surface and including a reentrant profile. A conformal electrically insulating layer that maintains the reentrant profile is in contact with the electrically conductive gate structure and at least a portion of the substrate. A conformal semiconductor layer that maintains the reentrant profile is in contact with the conformal electrically insulating layer. An electrode that extends into the reentrant profile is in contact with a first portion of the semiconductor layer. Another electrode is vertically spaced apart from the electrode, overlaps a portion of the electrode that extends into the reentrant profile, is in contact with a second portion of the semiconductor material layer over the top surface of the electrically conductive gate structure, and is within the reentrant profile.
摘要翻译：垂直晶体管包括基板和具有顶表面并且包括折入轮廓的导电栅极结构。维持凹凸轮廓的保形电绝缘层与导电栅极结构和衬底的至少一部分接触。保持凹凸轮廓的保形半导体层与保形电绝缘层接触。延伸到凹陷轮廓中的电极与半导体层的第一部分接触。另一个电极与电极垂直间隔开，与延伸到凹陷轮廓中的电极的一部分重叠，与导电栅极结构的顶表面上的半导体材料层的第二部分接触，并且位于可重入的资料

5. 发明授权

US09117914B1 VTFT with polymer core 有权
标题翻译： VTFT与聚合物芯
公开(公告)号：US09117914B1
公开(公告)日：2015-08-25
申请号：US14198628
申请日：2014-03-06
申请人： Carolyn Rae Ellinger , Shelby Forrester Nelson
发明人： Carolyn Rae Ellinger , Shelby Forrester Nelson
IPC分类号： H01L29/78 , H01L29/786
CPC分类号： H01L29/78642 , H01L29/78603 , H01L29/7869
摘要： A transistor includes a polymeric material post on a substrate. An inorganic material cap, covering the post, extends beyond an edge of the post to define a reentrant profile. A conformal conductive material gate layer is over the edge of the post in the reentrant profile. A conformal insulating material layer is on the gate layer in the reentrant profile. A conformal semiconductor material layer is on the insulating material layer in the reentrant profile. A first electrode is in contact with a first portion of the semiconductor layer over the cap. A second electrode is in contact with a second portion of the semiconductor layer over the substrate and not over the post, and adjacent to the edge of the post in the reentrant profile such that a distance between the first electrode and second electrode is greater than zero when measured orthogonally to the substrate surface.
摘要翻译：晶体管包括在基板上的聚合材料柱。覆盖柱的无机材料帽延伸超过柱的边缘以限定折返轮廓。保形导电材料栅极层位于折返轮廓中的柱的边缘上。在凹凸轮廓中的栅极层上保形绝缘材料层。保形半导体材料层位于折入型材中的绝缘材料层上。第一电极与帽上的半导体层的第一部分接触。第二电极与衬底上的半导体层的第二部分接触，而不是在柱上，并且邻近在折返轮廓中的柱的边缘，使得第一电极和第二电极之间的距离大于零当与基底表面正交测量时。

6. 发明授权

US09368491B2 Enhancement mode inverter with variable thickness dielectric stack 有权
标题翻译：具有可变厚度电介质叠层的增强型逆变器
公开(公告)号：US09368491B2
公开(公告)日：2016-06-14
申请号：US14526675
申请日：2014-10-29
申请人： Carolyn Rae Ellinger , Shelby Forrester Nelson
发明人： Carolyn Rae Ellinger , Shelby Forrester Nelson
IPC分类号： H01L29/786 , H01L27/088 , H01L27/07
CPC分类号： H01L27/0883 , H01L27/0705 , H01L27/1237 , H01L29/7869
摘要： An enhancement-mode inverter includes a load transistor and a drive transistor. The load transistor has a bottom gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness less than the load dielectric thickness. The first source is electrically connected to the second drain and the first gate is electrically connected to the first drain. The load gate dielectric and the drive gate dielectric are part of a common shared dielectric stack.
摘要翻译：增强型逆变器包括负载晶体管和驱动晶体管。负载晶体管具有底栅结构，其具有第一源极，第一漏极，负载沟道区域，第一半导体层以及第一栅极电极。负载栅极电介质位于负载沟道区域中，并具有负载介质厚度。驱动晶体管具有底栅结构，其具有第二源极，第二漏极，驱动沟道区，第二半导体层和第二栅电极。驱动栅极电介质位于驱动沟道区域中，并且具有小于负载电介质厚度的驱动电介质厚度。第一源电连接到第二漏极，并且第一栅极电连接到第一漏极。负载栅极电介质和驱动栅电介质是公共共用电介质叠层的一部分。

7. 发明授权

US09328418B2 Method of forming a patterned polymer layer 有权
标题翻译：形成图案化聚合物层的方法
公开(公告)号：US09328418B2
公开(公告)日：2016-05-03
申请号：US14487216
申请日：2014-09-16
申请人： Carolyn Rae Ellinger , Shelby Forrester Nelson
发明人： Carolyn Rae Ellinger , Shelby Forrester Nelson
IPC分类号： H01L21/469 , C23C16/455 , H01B19/04 , H01L21/314
CPC分类号： C23C16/45525 , C23C16/04 , H01B19/04 , H01L21/02554 , H01L21/02579 , H01L21/02642 , H01L21/3141 , H01L27/1248 , H01L29/42384 , H01L29/66742 , H01L29/78642 , H01L29/78648 , H01L29/7869
摘要： A method of producing a patterned polymeric insulator includes providing a substrate. A patterned polymeric inhibitor is provided on the substrate. An inorganic thin film is deposited using an atomic layer deposition process on the substrate in an area where the patterned polymeric inhibitor is absent. A material layer is deposited over the inorganic thin film and the patterned polymeric inhibitor.
摘要翻译：制造图案化聚合物绝缘体的方法包括提供衬底。在衬底上提供图案化的聚合物抑制剂。在不存在图案化聚合物抑制剂的区域中，使用原子层沉积工艺在基底上沉积无机薄膜。材料层沉积在无机薄膜和图案化聚合物抑制剂上。

8. 发明申请

US20150255626A1 VTFT WITH GATE ALIGNED TO VERTICAL STRUCTURE 有权
标题翻译： VTFT与门对齐到垂直结构
公开(公告)号：US20150255626A1
公开(公告)日：2015-09-10
申请号：US14198682
申请日：2014-03-06
申请人： Shelby Forrester Nelson , Carolyn Rae Ellinger , Mitchell Stewart Burberry
发明人： Shelby Forrester Nelson , Carolyn Rae Ellinger , Mitchell Stewart Burberry
IPC分类号： H01L29/786 , H01L29/06 , H01L29/49
CPC分类号： H01L29/78642 , H01L29/42384 , H01L29/66969 , H01L29/7869
摘要： A thin film transistor includes a post on a substrate. The post has a height dimension extending away from the substrate to a top portion of the post which extends a distance beyond a bottom portion of the post in a direction parallel to the substrate to define a reentrant profile. A conformal conductive gate layer is located on an edge of the post in the reentrant profile and not over the top portion of the post, and includes a portion that extends along the substrate. A conformal insulating layer is on the gate layer in the reentrant profile. A conformal semiconductor layer is on the insulating layer in the reentrant profile. First and second electrodes are located in contact with first and second portions of the semiconductor layer over the top portion of the post and not over the top portion of the post, respectively.
摘要翻译：薄膜晶体管包括在基板上的柱。该柱具有从衬底延伸到柱的顶部的高度尺寸，其在平行于衬底的方向上延伸超过柱的底部的距离以限定折返轮廓。共形导电栅极层位于柱的边缘中的折入轮廓中，而不是位于柱的顶部之上，并且包括沿着衬底延伸的部分。保形绝缘层位于折返轮廓中的栅极层上。保形半导体层位于凹凸轮廓中的绝缘层上。第一和第二电极分别与半导体层的第一和第二部分接触，位于柱的顶部上，而不分别位于柱的顶部。

9. 发明申请

US20150255623A1 VTFT WITH POST, CAP, AND ALIGNED GATE 有权
标题翻译： VTFT与POST，CAP和对齐门
公开(公告)号：US20150255623A1
公开(公告)日：2015-09-10
申请号：US14198633
申请日：2014-03-06
申请人： Shelby Forrester Nelson , Carolyn Rae Ellinger
发明人： Shelby Forrester Nelson , Carolyn Rae Ellinger
IPC分类号： H01L29/786 , H01L29/10 , H01L29/423
CPC分类号： H01L29/78642 , H01L29/1037 , H01L29/42384 , H01L29/7869
摘要： A thin film transistor includes a post on a substrate. The post has a height dimension extending away from the substrate to a top, and an edge along the height dimension. A cap covers the top of the post and extends to a distance beyond the edge of the post to define a reentrant profile. A conformal conductive gate layer is located on the edge of the post in the reentrant profile and not over the cap, and includes a portion that extends along the substrate. A conformal insulating layer is on the gate layer in the reentrant profile. A conformal semiconductor layer is on the insulating layer in the reentrant profile. First and second electrodes are located in contact with a first portion of the semiconductor layer over the cap and a second portion of the semiconductor layer not over the post, respectively.
摘要翻译：薄膜晶体管包括在基板上的柱。该柱具有从基板延伸到顶部的高度尺寸和沿着高度尺寸的边缘。帽盖覆盖柱的顶部并且延伸到距离柱的边缘的距离以定义可重入的轮廓。共形导电栅极层位于折返轮廓中的柱的边缘上并且不在盖上，并且包括沿着衬底延伸的部分。保形绝缘层位于折返轮廓中的栅极层上。保形半导体层位于凹凸轮廓中的绝缘层上。第一和第二电极分别与帽上的半导体层的第一部分接触并且半导体层的第二部分分别不在柱上。

10. 发明申请

US20150255579A1 VTFT FORMATION USING SELECTIVE AREA DEPOSITION 有权
标题翻译：使用选择区沉积的VTFT形成
公开(公告)号：US20150255579A1
公开(公告)日：2015-09-10
申请号：US14198636
申请日：2014-03-06
申请人： Shelby Forrester Nelson , Carolyn Rae Ellinger
发明人： Shelby Forrester Nelson , Carolyn Rae Ellinger
IPC分类号： H01L29/66 , H01L21/28
CPC分类号： H01L29/66742 , H01L29/42384 , H01L29/66969 , H01L29/78642 , H01L29/7869
摘要： A method of producing a vertical transistor includes providing a conductive gate structure having a reentrant profile on a substrate. A conformal insulating material layer is formed on the conductive gate structure. A conformal semiconductor material layer is formed on the insulating material layer. A deposition inhibiting material is deposited over a portion of the substrate and the conductive gate structure including filling the reentrant profile. A portion of the deposition inhibiting material is removed without removing all of the deposition inhibiting material from the reentrant profile. A plurality of electrodes is formed by depositing an electrically conductive material layer on portions of the semiconductor material layer using a selective area deposition process in which the electrically conductive material layer is not deposited on the deposition inhibiting material remaining in the reentrant profile.
摘要翻译：制造垂直晶体管的方法包括提供在衬底上具有折入轮廓的导电栅极结构。在导电栅结构上形成保形绝缘材料层。在绝缘材料层上形成保形半导体材料层。沉积抑制材料沉积在衬底的一部分上，并且导电栅极结构包括填充折入轮廓。除去沉积抑制材料的一部分，而不从所述折入轮廓中除去所有沉积抑制材料。通过使用选择性区域沉积工艺在半导体材料层的部分上沉积导电材料层来形成多个电极，其中导电材料层未沉积在残留在折入轮廓中的沉积抑制材料上。

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