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1. 发明授权

US07512916B2 Electrostatic discharge testing method and semiconductor device fabrication method 失效
标题翻译：静电放电测试方法和半导体器件制造方法
公开(公告)号：US07512916B2
公开(公告)日：2009-03-31
申请号：US11243355
申请日：2005-10-03
申请人： Sachio Hayashi
发明人： Sachio Hayashi
IPC分类号： G06F17/50 , H02H9/00
CPC分类号： G06F17/5036 , G01R31/002
摘要： A method for determining a layout which passes testing for electrostatic discharge in a semiconductor device, includes extracting an electrostatic discharge protection network including pads, nets and protective elements; setting start pads and end pads in the electrostatic discharge protection network; finding inter-pad voltages between the start pads and the end pads and electrostatic discharge current paths from the start pads to the end pads; grouping together the electrostatic discharge current paths in the same order; calculating estimated values of electrostatic discharge withstand voltages between the start pads and the end pads and groups to which the start pads and the end pads belong using a negative correlation between the inter-pad voltages and corresponding electrostatic withstand voltages; and determining whether the layout passes testing regarding electrostatic discharge.
摘要翻译：一种用于确定通过半导体器件中的静电放电测试的布局的方法，包括提取包括焊盘，网和保护元件的静电放电保护网络; 在静电放电保护网络中设置启动焊盘和端部焊盘; 在起始焊盘和端部焊盘之间找到衬垫间电压，以及从起始焊盘到端部焊盘的静电放电电流路径; 以相同的顺序将静电放电电流路径分组在一起; 使用垫间电压和相应的静电耐受电压之间的负相关来计算起始焊盘和起始焊盘和端部焊盘所属的端部焊盘和组之间的静电放电耐受电压的估计值; 以及确定布局是否通过关于静电放电的测试。

2. 发明授权

US07114137B2 Method of analyzing semiconductor LSI circuit electrostatic discharge 有权
标题翻译：分析半导体LSI电路静电放电的方法
公开(公告)号：US07114137B2
公开(公告)日：2006-09-26
申请号：US10872179
申请日：2004-06-17
申请人： Sachio Hayashi
发明人： Sachio Hayashi
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An electrostatic discharge analysis method includes extracting the pads from an input layout of the semiconductor integrated circuit; extracting the nets connected to the extracted pads; extracting the protective elements connected to the extracted nets; forming connection nodes that connect the pads or the protective elements to the nets; extracting for each net, distributed resistances that distribute along the net; connecting the distributed resistances to the connection nodes in place of the nets; forming inter-resistance nodes between the distributed resistances; and calculating an inter-pad voltage when flowing electrostatic discharge current between the pads.
摘要翻译：静电放电分析方法包括从半导体集成电路的输入布局中提取焊盘; 提取连接到提取的垫的网; 提取与提取的网络相连的保护元件; 形成将焊盘或保护元件连接到网的连接节点; 提取每个网络，分布在网络上的分布式电阻; 将分布式电阻连接到连接节点而不是网络; 形成分布电阻之间的电阻间节点; 以及当在所述焊盘之间流动静电放电电流时计算衬垫间电压。

3. 发明授权

US06842727B1 Device and method for analyzing EMI noise and semiconductor device 有权
标题翻译：用于分析EMI噪声和半导体器件的器件和方法
公开(公告)号：US06842727B1
公开(公告)日：2005-01-11
申请号：US09453966
申请日：1999-12-03
申请人： Sachio Hayashi
发明人： Sachio Hayashi
IPC分类号： G01R29/08 , G06F17/50 , H01L21/66
CPC分类号： G06F17/5036
摘要： A technique for effectively attenuating EMI noise, which is generated from the electric power system of semiconductor devices, is described. In accordance with the technique, a power supply netlist with an additional electric current source(s) is generated by adding block power supply current waveform data, as extracted from test vector data and a block netlist, to the power supply netlist as extracted from the layout data of the circuit under analysis. A circuit simulation of the power supply netlist with an additional electric current source(s) is then performed in order to calculate power supply current/voltage waveform data. Furthermore, current/voltage spectral data is calculated by the Fourier transformation of the power supply current/voltage waveform data followed by displaying the current/voltage spectral data as the result of the Fourier transformation.
摘要翻译：描述了从半导体装置的电力系统产生的有效衰减EMI噪声的技术。根据该技术，通过将从测试矢量数据和块网表提取的块电源电流波形数据与从电源网络列表提取的电源网表相加，生成具有附加电流源的电源网表电路布局数据分析。然后执行具有附加电流源的电源网表的电路仿真，以便计算电源电流/电压波形数据。此外，电流/电压谱数据通过电源电流/电压波形数据的傅里叶变换计算，随后作为傅立叶变换的结果显示当前/电压谱数据。

4. 发明授权

US5746304A Speed increasing and accumulating conveyor chain 失效
标题翻译：增速输送链
公开(公告)号：US5746304A
公开(公告)日：1998-05-05
申请号：US561177
申请日：1995-11-20
申请人： Michiya Hashino , James G. Lamoureux , Shinichi Fukushima , Katsutoshi Shibayama , Yoshihiro Murakami , Sachio Hayashi
发明人： Michiya Hashino , James G. Lamoureux , Shinichi Fukushima , Katsutoshi Shibayama , Yoshihiro Murakami , Sachio Hayashi
IPC分类号： B65G17/24 , B65G47/26 , B65G13/06
CPC分类号： B65G47/268 , B65G17/24 , B65G2201/02
摘要： The speed increasing and accumulating conveyor chain of the present invention can convey a conveyed object faster than the running speed of the chain, and keep the conveyed object stopped while continuously running the chain itself. The load roller with a larger diameter and the running roller with a smaller diameter are coaxially and rotatably mounted on the connecting pin, which is secured to the link plate, respectively. The frictional material is mounted on the load surface of the load roller, wherein the frictional material provides the load surface of the load roller with a larger frictional force than that of rotatable surface between the load roller and the running roller.
摘要翻译：本发明的增速输送链可以使输送物体比链条的运行速度更快地传送，并且在连续运转链条本身的同时保持被输送物体停止。具有较大直径的装载辊和较小直径的行进辊同轴且可旋转地安装在连接销上，该连接销分别固定在连接板上。摩擦材料安装在负载辊的负载表面上，其中摩擦材料使负载辊的负载表面具有比负载辊和运行辊之间的可旋转表面更大的摩擦力。

5. 发明申请

US20110295536A1 CLOCK JITTER ANALYZING METHOD AND APPARATUS 审中-公开
标题翻译：时钟抖动分析方法和装置
公开(公告)号：US20110295536A1
公开(公告)日：2011-12-01
申请号：US12982739
申请日：2010-12-30
申请人： Tomoyuki YODA , Takuma AOYAMA , Sachio HAYASHI
发明人： Tomoyuki YODA , Takuma AOYAMA , Sachio HAYASHI
IPC分类号： G06F19/00 , G01R29/00
CPC分类号： G01R31/31709
摘要： There is provided a method for analyzing a jitter of a clock flowing in a clock path inside a semiconductor integrated circuit. Elements, which belong to any clock domains except for a selected clock domain among operation scenario information, are brought into a halting state, to create a domain operation scenario. Using the domain operation scenario, a power-supply noise analysis is performed on a clock used in the selected clock domain for a period of one to several cycles, to obtain a domain power-supply noise waveform. The obtained waveform is repeatedly connected, to create a cyclic waveform. Part of the cyclic waveform is halted, to obtain a processed domain power-supply noise waveform. The processed domain power-supply noise waveform obtained with respect to each clock domain is superimposed, to create a power-supply noise waveform. Based on the created waveform, a jitter of the clock flowing in the clock path is calculated.
摘要翻译：提供了一种用于分析在半导体集成电路内的时钟路径中流动的时钟的抖动的方法。属于操作场景信息中所选择的时钟域之外的任何时钟域的元素被进入停止状态，以创建域操作场景。使用域操作场景，对所选择的时钟域中使用的时钟进行一到多个周期的电源噪声分析，以获得域电源噪声波形。获得的波形被重复连接，以产生循环波形。部分循环波形停止，以获得处理域电源噪声波形。相对于每个时钟域获得的处理域电源噪声波形被叠加，以产生电源噪声波形。基于创建的波形，计算在时钟路径中流动的时钟的抖动。

6. 发明授权

US07340699B2 Analysis apparatus for semiconductor LSI circuit electrostatic discharge by calculating inter-pad voltage between pads 有权
标题翻译：用于通过计算焊盘之间的垫间电压的半导体LSI电路静电放电的分析装置
公开(公告)号：US07340699B2
公开(公告)日：2008-03-04
申请号：US10890025
申请日：2004-07-12
申请人： Sachio Hayashi
发明人： Sachio Hayashi
IPC分类号： G06F17/50 , H01L23/62
CPC分类号： H01L27/0288 , H01L27/0292
摘要： A semiconductor integrated circuit electrostatic discharge analysis apparatus includes a resistance network generation unit generating a resistance network served as a power supply interconnect equivalent circuit in a logic cell region of a semiconductor LSI circuit based on pitch, width and a sheet resistance of a power supply interconnect; a protection network generation unit generating an electrostatic discharge protection network with pads and protection elements placed in an I/O cell region of the changing semiconductor LSI circuit, connected to the resistance network; and an analysis unit calculating an inter-pad voltage between the pads when electrostatic discharge equivalent current flows between the pads.
摘要翻译：半导体集成电路静电放电分析装置包括电阻网络生成单元，其基于间距，宽度和电源互连的薄层电阻，在半导体LSI电路的逻辑单元区域中产生用作电源互连等效电路的电阻网络 ; 保护网络生成单元，其生成静电放电保护网络，其具有连接到所述电阻网络的位于所述变化的半导体LSI电路的I / O单元区域中的焊盘和保护元件; 以及分析单元，当静电放电等效电流在焊盘之间流动时，计算焊盘之间的焊盘间电压。

7. 发明授权

US5663892A Method of compacting layouts of semiconductor integrated circuit designed in a hierarchy 失效
标题翻译：压实层级设计的半导体集成电路布局的方法
公开(公告)号：US5663892A
公开(公告)日：1997-09-02
申请号：US412503
申请日：1995-03-29
申请人： Sachio Hayashi , Tyusei Ogawa
发明人： Sachio Hayashi , Tyusei Ogawa
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L27/04
CPC分类号： G06F17/5081
摘要： A method for performing compaction of a layout of a semiconductor integrated circuit designed in a hierarchy is described. The compaction of the layout is carried out by repeating a single level compaction process for compacting cell layouts in one of the hierarchical levels from a lowest level to a highest level of the hierarchical levels. The single level compaction process comprises a first replacement step of replacing lower level cell layouts in a current level cell layout with abstract cell layouts having the same profile and the same positions of terminals to be connected to the current level cell layout as the lower level cell layouts have in advance of compaction. The compaction of the current level cell is performed under a constraint that the relocations of the terminals of the current level cell layout after compaction from the original positions before compaction are possible within prescribed ranges. After compaction, the abstract cell layouts is replaced by the lower level cell layouts.
摘要翻译：描述了一种用于执行层次化设计的半导体集成电路的布局压缩的方法。布局的压缩是通过重复单层压缩过程来实现的，从而将层次级别中的一个层级中的单层布局压缩成层级级别的最低级别。单级压缩处理包括第一替换步骤，用当前级单元布局替换下一级单元格布局，其中抽象单元格布局具有与下一层单元相同的轮廓和要连接到当前级单元布局的相同位置的终端布局在压实之前。在压缩之前的当前级别单元布局的端子从压实前的原始位置的重定位在规定范围内可能的约束下执行当前级单元的压缩。压缩后，抽象单元格布局被较低级别的单元格布局所替代。

8. 发明授权

US4956417A Nitrile group-containing highly saturated copolymer rubber and rubber composition having improved cold resistance 失效
标题翻译：含有腈基的高度饱和的共聚物橡胶和具有改善的耐寒性的橡胶组合物
公开(公告)号：US4956417A
公开(公告)日：1990-09-11
申请号：US326862
申请日：1989-03-21
申请人： Sachio Hayashi , Yoichiro Kubo , Noboru Watanabe , Yoshiaki Aimura
发明人： Sachio Hayashi , Yoichiro Kubo , Noboru Watanabe , Yoshiaki Aimura
IPC分类号： C08L15/00 , C08C19/02 , C08F236/12 , C08L9/02 , C08L15/02 , C08L21/00 , C08L33/18
CPC分类号： C08C19/02 , C08F236/12
摘要： A nitrile group-containing, highly saturated copolymer rubber is disclosed, the copolymer chain of which is comprised of (1) 5 to 40% by weight of units of an unsaturated nitrile monomer, (2) 1 to 80% by weight of units of a monomer selected from a fluorine-free unsaturated carboxylic acid ester monomer and a fluorine-containing vinyl monomer and (3) up to 20% by weight of units of a conjugated diene monomer, with the balance being (4) units of a hydrogenated conjugated diene monomer, wherein the sum of the contents of the monomer units (1) and (2) is 30 to 90% and the sum of the contents of the monomer units (3) and (4) is 10 to 70% by weight. This copolymer rubber results in a rubber composition having an improved cold resistance.
摘要翻译：公开了含腈基的高度饱和的共聚物橡胶，其共聚物链由（1）5〜40重量％的不饱和腈单体单元组成，（2）1〜80重量％选自不含氟的不饱和羧酸酯单体和含氟乙烯基单体的单体和（3）至多20重量％的共轭二烯单体单元，余量为（4）单元的氢化共轭二烯单体，其中单体单元（1）和（2）的含量之和为30〜90％，单体单元（3）和（4）的含量之和为10〜70重量％。该共聚物橡胶得到耐寒性提高的橡胶组合物。

9. 发明申请

US20060109596A1 Electrostatic discharge testing method and semiconductor device fabrication method 失效
公开(公告)号：US20060109596A1
公开(公告)日：2006-05-25
申请号：US11243355
申请日：2005-10-03
申请人： Sachio Hayashi
发明人： Sachio Hayashi
IPC分类号： H02H9/00
CPC分类号： G06F17/5036 , G01R31/002
摘要： A method for determining a layout which passes testing for electrostatic discharge in a semiconductor device, includes extracting an electrostatic discharge protection network including pads, nets and protective elements; setting start pads and end pads in the electrostatic discharge protection network; finding inter-pad voltages between the start pads and the end pads and electrostatic discharge current paths from the start pads to the end pads; grouping together the electrostatic discharge current paths in the same order; calculating estimated values of electrostatic discharge withstand voltages between the start pads and the end pads and groups to which the start pads and the end pads belong using a negative correlation between the inter-pad voltages and corresponding electrostatic withstand voltages; and determining whether the layout passes testing regarding electrostatic discharge.

10. 发明申请

US20050146380A1 Analysis apparatus for semiconductor LSI circuit 有权
标题翻译：半导体LSI电路分析装置
公开(公告)号：US20050146380A1
公开(公告)日：2005-07-07
申请号：US10890025
申请日：2004-07-12
申请人： Sachio Hayashi
发明人： Sachio Hayashi
IPC分类号： G06F17/50 , H01L21/82 , H01L27/02 , H03F1/26 , H03F1/30
CPC分类号： H01L27/0288 , H01L27/0292
摘要： A semiconductor integrated circuit electrostatic discharge analysis apparatus includes a resistance network generation unit generating a resistance network served as a power supply interconnect equivalent circuit in a logic cell region of a semiconductor LSI circuit based on pitch, width and a sheet resistance of a power supply interconnect; a protection network generation unit generating an electrostatic discharge protection network with pads and protection elements placed in an I/O cell region of the changing semiconductor LSI circuit, connected to the resistance network; and an analysis unit calculating an inter-pad voltage between the pads when electrostatic discharge equivalent current flows between the pads.
摘要翻译：半导体集成电路静电放电分析装置包括电阻网络生成单元，其基于间距，宽度和电源互连的薄层电阻，在半导体LSI电路的逻辑单元区域中产生用作电源互连等效电路的电阻网络 ; 保护网络生成单元，其生成静电放电保护网络，其具有连接到所述电阻网络的位于所述变化的半导体LSI电路的I / O单元区域中的焊盘和保护元件; 以及分析单元，当静电放电等效电流在焊盘之间流动时，计算焊盘之间的焊盘间电压。

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