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1. 发明授权

US09007819B2 Magnetic random access memory device and method of writing data therein 有权
标题翻译：磁性随机存取存储器件及其中的数据写入方法
公开(公告)号：US09007819B2
公开(公告)日：2015-04-14
申请号：US13532811
申请日：2012-06-26
申请人： Su-Jin Ahn , Kyung-Tae Nam
发明人： Su-Jin Ahn , Kyung-Tae Nam
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/1675 , G11C11/161
摘要： In a method of writing data in an MRAM device, a first operation unit is selected in a plurality of memory cells of the MRAM device. First to n-th switching pulses are sequentially applied to the first operation unit to write data in first to n-th groups of memory cells of the first operation unit, respectively. The n-th switching pulse may have a current level lower than that of an (n−1)th switching pulse, where n is an integer larger than at least 1. The n-th switching pulse may have a pulse width narrower than that of an (n−1)th switching pulse, where n is an integer larger than at least 1. The technique can be repeated for a second operation unit. A device and system are disclosed in which different current switching pulses are applied to multiple groups of memory cells within the first and/or second operation units.
摘要翻译：在MRAM装置中写入数据的方法中，在MRAM装置的多个存储单元中选择第一操作单元。第一至第n开关脉冲被顺序地施加到第一操作单元以分别在第一操作单元的第一至第n组存储单元中写入数据。第n开关脉冲的电流电平可以低于第（n-1）个开关脉冲的电流电平，其中n是大于至少1的整数。第n个开关脉冲的脉冲宽度可以窄于的第（n-1）个开关脉冲，其中n是大于至少1的整数。可以对第二操作单元重复该技术。公开了一种装置和系统，其中不同的电流切换脉冲被施加到第一和/或第二操作单元内的多组存储器单元。

2. 发明授权

US08610192B2 Non-volatile memory devices having charge storage layers at intersecting locations of word lines and active regions 有权
标题翻译：在字线和有源区域的相交位置处具有电荷存储层的非易失性存储器件
公开(公告)号：US08610192B2
公开(公告)日：2013-12-17
申请号：US13173759
申请日：2011-06-30
申请人： Won-Cheol Jeong , Su-Jin Ahn , Yoon-Moon Park
发明人： Won-Cheol Jeong , Su-Jin Ahn , Yoon-Moon Park
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/66833 , H01L29/792
摘要： A non-volatile memory device can include a plurality of parallel active regions that are defined by a plurality of device isolation layers formed on a semiconductor substrate, where each of the plurality of parallel active regions extends in a first direction and has a top surface and sidewalls. A plurality of parallel word lines can extend in a second direction and cross over the plurality of parallel active regions at intersecting locations. A plurality of charge storage layers can be disposed at the intersecting locations between the plurality of parallel active regions and the plurality of parallel word lines. Each of the plurality of charge storage layers at the intersecting locations can have a first side and a second side that is parallel to the second direction and can have a first length, a third side and a fourth side that are parallel to the first direction and can have a second length, where the first length is less than the second length.
摘要翻译：非易失性存储器件可以包括由形成在半导体衬底上的多个器件隔离层限定的多个平行有源区，其中多个平行有源区中的每一个在第一方向上延伸并且具有顶表面和侧壁多个平行字线可以在第二方向上延伸并且在交叉位置处跨越多个平行的有效区域。多个电荷存储层可以设置在多个平行有源区和多个平行字线之间的交叉位置处。在交叉位置处的多个电荷存储层中的每一个可以具有平行于第二方向的第一侧和第二侧，并且可以具有平行于第一方向的第一长度，第三侧和第四侧，可以具有第二长度，其中第一长度小于第二长度。

3. 发明授权

US07482616B2 Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权
标题翻译：具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法
公开(公告)号：US07482616B2
公开(公告)日：2009-01-27
申请号：US11139283
申请日：2005-05-27
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L29/02
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.
摘要翻译：在一个实施例中，相变存储器件具有防止存储器单元污染或氧化的氧化阻挡层及其制造方法。在一个实施例中，半导体存储器件包括覆盖半导体衬底的成型层。模制层具有从其顶表面垂直延伸的突出部分。该装置还包括与突出部分相邻的相变材料图案和与相变材料图案电连接的下部电极。

4. 发明授权

US07440308B2 Phase-change random access memory device and method of operating the same 有权
标题翻译：相变随机存取存储器件及其操作方法
公开(公告)号：US07440308B2
公开(公告)日：2008-10-21
申请号：US11515422
申请日：2006-09-05
申请人： Chang Wook Jeong , Su-Youn Lee , Won-Cheol Jeong , Jae-Hyun Park , Su-Jin Ahn , Fai Yeung
发明人： Chang Wook Jeong , Su-Youn Lee , Won-Cheol Jeong , Jae-Hyun Park , Su-Jin Ahn , Fai Yeung
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C2213/79
摘要： A phase-change random access memory device may include a phase-change pattern, a first electrode structure connected to the phase-change pattern, and a second electrode structure spaced apart from the first electrode structure and connected to the phase-change pattern, wherein at least one of the first electrode structure and the second electrode structure includes a plurality of resistor patterns connected to the phase-change pattern in parallel.
摘要翻译：相变随机存取存储器件可以包括相变图案，连接到相变图案的第一电极结构和与第一电极结构间隔开并连接到相变图案的第二电极结构，其中第一电极结构和第二电极结构中的至少一个包括并联连接到相变图案的多个电阻图案。

5. 发明申请

US20080085581A1 Methods of forming a semiconductor device that allow patterns in different regions that have different pitches to be connected 有权
公开(公告)号：US20080085581A1
公开(公告)日：2008-04-10
申请号：US11647722
申请日：2006-12-29
申请人： Jin-Ho Kim , Jae-Kwan Park , Dong-Hwa Kwak , Su-Jin Ahn , Yoon-Moon Park , Jue-Hwang Sim , Jang-Ho Park , Sang-Yong Park
发明人： Jin-Ho Kim , Jae-Kwan Park , Dong-Hwa Kwak , Su-Jin Ahn , Yoon-Moon Park , Jue-Hwang Sim , Jang-Ho Park , Sang-Yong Park
IPC分类号： H01L21/8242
CPC分类号： H01L27/11568 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/105
摘要： Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with a second pitch in the second region that are alternately arranged with the first patterns, forming a space insulating layer that covers the first and second patterns and comprises gap regions that are alternately arranged with the first patterns so as to correspond with the second patterns, forming third patterns that correspond to the second patterns in the gap regions, respectively, etching the space insulating layer between the first and second patterns and between the first and third patterns, such that the space insulating layer remains between the second patterns and the third patterns, and etching the lower layer using the first, second, and third patterns and the remaining space insulating layer between the second and third patterns as an etching mask.

6. 发明申请

US20070228445A1 NON-VOLATILE MEMORY DEVICES 有权
标题翻译：非易失性存储器件
公开(公告)号：US20070228445A1
公开(公告)日：2007-10-04
申请号：US11613345
申请日：2006-12-20
申请人： Won-Cheol Jeong , Su-Jin Ahn , Yoon-Moon Park
发明人： Won-Cheol Jeong , Su-Jin Ahn , Yoon-Moon Park
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/66833 , H01L29/792
摘要： Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction. Devices may also include word lines that may cross over the active regions and extend in a second direction intersecting the first direction. The active regions have a first pitch and the word lines have a second pitch that is greater than the first pitch.
摘要翻译：提供非易失性存储器件。器件包括可由形成在半导体衬底上并沿第一方向延伸的器件隔离层限定的有源区。设备还可以包括字线，其可以跨越有效区域并且沿与第一方向相交的第二方向延伸。有源区具有第一间距，并且字线具有大于第一间距的第二间距。

7. 发明申请

US20060076548A1 PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same 有权
标题翻译：具有多个有序区域的垂直位置的PRAM及其形成方法
公开(公告)号：US20060076548A1
公开(公告)日：2006-04-13
申请号：US11246863
申请日：2005-10-07
申请人： Jae-Hyun Park , Hyeong-Geun An , Su-Jin Ahn , Yoon-Jong Song , Hyung-Joo Youn , Kyu-Chul Kim
发明人： Jae-Hyun Park , Hyeong-Geun An , Su-Jin Ahn , Yoon-Jong Song , Hyung-Joo Youn , Kyu-Chul Kim
IPC分类号： H01L29/02
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/144
摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.
摘要翻译：提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。其他半导体衬底分别限定其它有源区。在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。

8. 发明授权

US06949783B2 Memory cell transistor having different source/drain junction profiles connected to DC node and BC node and manufacturing method thereof 有权
标题翻译：存储单元晶体管具有连接到DC节点和BC节点的不同的源极/漏极结型材及其制造方法
公开(公告)号：US06949783B2
公开(公告)日：2005-09-27
申请号：US10235142
申请日：2002-09-05
申请人： Su-jin Ahn
发明人： Su-jin Ahn
IPC分类号： H01L27/108 , H01L21/336 , H01L21/8242 , H01L29/78 , H01L29/76
CPC分类号： H01L27/10873 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A memory cell transistor of a DRAM device is provided. A gate stack pattern is formed on a semiconductor substrate. A DC node and a BC node are formed substantially under lateral sides of the gate stack pattern in the semiconductor substrate. The DC node and the BC node are being electrically connected to a bit line and a storage electrode of a capacitor respectively. A first source/drain junction region is formed under the DC node and a second source/drain junction region is formed under the BC node. The first source/drain junction region has a profile which is different from that of the second source/drain junction region.
摘要翻译：提供DRAM器件的存储单元晶体管。在半导体衬底上形成栅堆叠图案。 DC节点和BC节点基本上形成在半导体衬底中的栅堆叠图案的侧面下方。 DC节点和BC节点分别电连接到电容器的位线和存储电极。第一源极/漏极结区域形成在DC节点下方，并且在BC节点下方形成第二源极/漏极结区域。第一源极/漏极结区域具有与第二源极/漏极结区域不同的轮廓。

9. 发明申请

US20210335431A1 NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD OF A NON-VOLATILE MEMORY DEVICE 有权
公开(公告)号：US20210335431A1
公开(公告)日：2021-10-28
申请号：US15405346
申请日：2017-01-13
申请人： CHANG-MIN CHOI , BONG-YONG LEE , DONG-CHAN KIM , SU-JIN AHN
发明人： CHANG-MIN CHOI , BONG-YONG LEE , DONG-CHAN KIM , SU-JIN AHN
IPC分类号： G11C16/34 , G11C16/10 , G11C16/28 , G11C16/30 , G11C16/08 , G11C16/32
摘要： A method of programming a non-volatile memory includes executing at least two program loops on memory cells in a selected word line, generating a fail bit trend based on a result of executing each of the at least two program loops, predicting a plurality of program loops comprising an N program loop to be executed last on the memory cells, based on the generated fail bit trend, and changing, based on a result of predicting the plurality of program loops, a level of an N program voltage provided to the memory cells when the N program loop is executed.

10. 发明申请

US20170125439A1 VERTICAL MEMORY DEVICES 审中-公开
公开(公告)号：US20170125439A1
公开(公告)日：2017-05-04
申请号：US15223255
申请日：2016-07-29
申请人： CHANG-MIN CHOI , JU-YOUNG LIM , SU-JIN AHN
发明人： CHANG-MIN CHOI , JU-YOUNG LIM , SU-JIN AHN
IPC分类号： H01L27/115 , H01L23/528
CPC分类号： H01L27/11582 , H01L23/5283 , H01L27/0688 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578
摘要： A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

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