专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090044078A1 ECC FUNCTIONAL BLOCK PLACEMENT IN A MULTI-CHANNEL MASS STORAGE DEVICE 有权
标题翻译：多通道大容量存储设备中的ECC功能块放置
公开(公告)号：US20090044078A1
公开(公告)日：2009-02-12
申请号：US11835878
申请日：2007-08-08
申请人： Andrew Vogan , Jawad B. Khan , Sowmiya Jayachandran
发明人： Andrew Vogan , Jawad B. Khan , Sowmiya Jayachandran
IPC分类号： G06F11/16 , H03M13/15
CPC分类号： G11B20/18 , G06F11/108 , G11B20/10527 , G11B2020/1062
摘要： A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.
摘要翻译：多通道存储设备可以包括主机控制器，以从主机设备和缓冲存储器接收输入数据，以在下游存储之前存储输入数据和相关联的纠错数据。缓冲存储器下游的多个存储通道可以将输入数据和相关联的纠错数据存储在非易失性存储介质上的至少一个存储通道中。主机控制器和缓冲存储器之间的纠错引擎可以对来自主机设备的输入数据执行纠错编码，以产生相关联的纠错数据以存储在缓冲存储器中。这种纠错引擎可以防止缓冲存储器和存储信道中的数据错误。

2. 发明申请

US20160189757A1 MANAGING DISTURBANCE INDUCED ERRORS 有权
标题翻译：管理干扰引起的错误
公开(公告)号：US20160189757A1
公开(公告)日：2016-06-30
申请号：US14938221
申请日：2015-11-11
申请人： PRASHANT S. DAMLE , FRANK T. HADY , PAUL D. RUBY , KIRAN PANGAL , SOWMIYA JAYACHANDRAN
发明人： PRASHANT S. DAMLE , FRANK T. HADY , PAUL D. RUBY , KIRAN PANGAL , SOWMIYA JAYACHANDRAN
IPC分类号： G11C7/10 , G11C11/406
CPC分类号： G11C7/1072 , G11C11/406 , G11C11/40618 , G11C16/3431
摘要： In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
摘要翻译：在一个实施例中，存储器控制器可以确定与存储器件中的目标存储器单元相关联的一个或多个相邻存储器单元将被刷新。控制器可以生成与刷新一个或多个相邻存储器单元相关联的命令。控制器可以将命令从存储器控制器传送到包含目标存储器单元的存储器件。命令可以指示存储器设备刷新相邻存储器单元和/或返回与相邻存储器单元相关联的一个或多个地址。

3. 发明授权

US09417684B2 Mechanism for facilitating power and performance management of non-volatile memory in computing devices 有权
标题翻译：促进计算设备中非易失性存储器的功率和性能管理的机制
公开(公告)号：US09417684B2
公开(公告)日：2016-08-16
申请号：US13977515
申请日：2011-12-22
申请人： Simon D. Ramage , Jason A. Gayman , Joerg Hartung , Curtis A. Gittens , Sowmiya Jayachandran , Richard P. Mangold
发明人： Simon D. Ramage , Jason A. Gayman , Joerg Hartung , Curtis A. Gittens , Sowmiya Jayachandran , Richard P. Mangold
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： A mechanism is described for facilitating power governance of non-volatile memory devices using a power governing mechanism employed at a computing device according to one embodiment of the invention. A method of embodiments of the invention includes maintaining a credit pool having a plurality of credits to be released to a plurality of memory channels associated with a plurality of non-volatile memory devices. The plurality of credits may be used to provide sufficient power to perform memory operations associated with a computing device. The method may further include receiving a credit request having a petition to obtain one or more credits for a memory channel of the plurality of memory channels to facilitate performance of a memory operation, determining whether the one or more credits are available in the credit pool, and retrieving the one or more credits from the credit pool, if the one or more credits are available in the credit pool. The method may further include releasing the one or more credits to the memory channel. The one or more released credits are used to perform the memory operation.
摘要翻译：描述了一种机构，其用于使用根据本发明的一个实施例的在计算设备处采用的功率调节机构来促进非易失性存储器件的功率治理。本发明的实施例的方法包括维持具有要被释放到与多个非易失性存储器设备相关联的多个存储器通道的多个信用的信用卡。多个信用可以用于提供足够的电力来执行与计算设备相关联的存储器操作。该方法还可以包括接收具有请求的信用请求，以获得多个存储器通道中的存储器通道的一个或多个信用以促进存储器操作的执行，确定信用库中的一个或多个信用是否可用，以及如果信用卡中的一个或多个信用可用，则从信用卡中检索一个或多个信用。该方法还可以包括将一个或多个信用释放到存储器通道。一个或多个释放的积分用于执行存储器操作。

4. 发明申请

US20090172213A1 COMMAND COMPLETION DETECTION IN A MASS STORAGE DEVICE 审中-公开
标题翻译：大容量存储设备中的命令完成检测
公开(公告)号：US20090172213A1
公开(公告)日：2009-07-02
申请号：US11968042
申请日：2007-12-31
申请人： Sowmiya Jayachandran , Jawad B. Khan , Randall K. Webb , Robert W. Faber
发明人： Sowmiya Jayachandran , Jawad B. Khan , Randall K. Webb , Robert W. Faber
IPC分类号： G06F3/00
CPC分类号： G06F3/0659 , G06F3/0625 , G06F3/0679 , Y02D10/154
摘要： In some embodiments, after a hold off time following issuance of a memory command has elapsed, a status read operation is performed to determine a status of the memory command. In some embodiments, if the memory command has not yet completed, a polling interval is used to perform a status read operation to determine the status of the memory command after the polling interval has expired, and repeating the process until the memory command has been completed. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，在发出存储器命令之后的停止时间过去之后，执行状态读取操作以确定存储器命令的状态。在一些实施例中，如果存储器命令尚未完成，则轮询间隔被用于执行状态读取操作以在轮询间隔期满之后确定存储器命令的状态，并重复该过程直到存储器命令已经完成。描述和要求保护其他实施例。

5. 发明申请

US20140281203A1 MANAGING DISTURBANCE INDUCED ERRORS 有权
标题翻译：管理干扰引起的错误
公开(公告)号：US20140281203A1
公开(公告)日：2014-09-18
申请号：US13832278
申请日：2013-03-15
申请人： PRASHANT S. DAMLE , FRANK T. HADY , PAUL D. RUBY , KIRAN PANGAL , SOWMIYA JAYACHANDRAN
发明人： PRASHANT S. DAMLE , FRANK T. HADY , PAUL D. RUBY , KIRAN PANGAL , SOWMIYA JAYACHANDRAN
IPC分类号： G11C11/406
CPC分类号： G11C7/1072 , G11C11/406 , G11C11/40618 , G11C16/3431
摘要： In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
摘要翻译：在一个实施例中，存储器控制器可以确定与存储器件中的目标存储器单元相关联的一个或多个相邻存储器单元将被刷新。控制器可以生成与刷新一个或多个相邻存储器单元相关联的命令。控制器可以将命令从存储器控制器传送到包含目标存储器单元的存储器件。命令可以指示存储器设备刷新相邻存储器单元和/或返回与相邻存储器单元相关联的一个或多个地址。

6. 发明授权

US08001444B2 ECC functional block placement in a multi-channel mass storage device 有权
标题翻译： ECC功能块放置在多通道大容量存储设备中
公开(公告)号：US08001444B2
公开(公告)日：2011-08-16
申请号：US11835878
申请日：2007-08-08
申请人： Andrew Vogan , Jawad B. Khan , Sowmiya Jayachandran
发明人： Andrew Vogan , Jawad B. Khan , Sowmiya Jayachandran
IPC分类号： G11C29/00
CPC分类号： G11B20/18 , G06F11/108 , G11B20/10527 , G11B2020/1062
摘要： A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.
摘要翻译：多通道存储设备可以包括主机控制器，以从主机设备和缓冲存储器接收输入数据，以在下游存储之前存储输入数据和相关联的纠错数据。缓冲存储器下游的多个存储通道可以将输入数据和相关联的纠错数据存储在非易失性存储介质上的至少一个存储通道中。主机控制器和缓冲存储器之间的纠错引擎可以对来自主机设备的输入数据执行纠错编码，以产生相关联的纠错数据以存储在缓冲存储器中。这种纠错引擎可以防止缓冲存储器和存储信道中的数据错误。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式