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1. 发明授权

US08390633B2 Memory for providing a graphic content 有权
标题翻译：用于提供图形内容的内存
公开(公告)号：US08390633B2
公开(公告)日：2013-03-05
申请号：US11771834
申请日：2007-06-29
申请人： Christoph Bilger , Rex Kho , Achim Schramm , Martin Maier , Yann Zinzius , Armin Kohlhase
发明人： Christoph Bilger , Rex Kho , Achim Schramm , Martin Maier , Yann Zinzius , Armin Kohlhase
IPC分类号： G06T1/60
CPC分类号： G09G5/395 , G06T1/60
摘要： A memory device comprises a memory array and a processing device. The memory array is configured to store a graphic data set. The processing device is configured to initiate outputting of data of the graphic data set from the memory array and to combine the outputted data in response to a read request for providing a graphic content.
摘要翻译：存储器件包括存储器阵列和处理器件。存储器阵列被配置为存储图形数据集。处理装置被配置为响应于用于提供图形内容的读取请求，启动从存储器阵列输出图形数据集的数据并组合输出的数据。

2. 发明申请

US20090024806A1 STORAGE DEVICE, STORAGE CONTROLLER, SYSTEM, METHOD OF STORING DATA, METHOD OF READING DATA AND FILE SYSTEM 审中-公开
标题翻译：存储设备，存储控制器，系统，存储数据的方法，读取数据和文件系统的方法
公开(公告)号：US20090024806A1
公开(公告)日：2009-01-22
申请号：US11781039
申请日：2007-07-20
申请人： CHRISTOPH BILGER , Rex Kho , Achim Schramm , Martin Maier , Yann Zinzius , Armin Kohlhase
发明人： CHRISTOPH BILGER , Rex Kho , Achim Schramm , Martin Maier , Yann Zinzius , Armin Kohlhase
IPC分类号： G06F13/38 , G06F17/30
CPC分类号： G06F3/0661 , G06F3/0607 , G06F3/0679
摘要： A storage device comprises a storage location, an interface coupled to the storage location, and a data conversion circuit coupled to the storage location and to the interface. The interface is configured for an exchange of data between the storage device and external circuitry coupled to the interface. The data conversion circuit is configured for converting data from a first data format to a second data format. The data conversion circuit is configured to convert at least one of data read from the storage location before they are transferred to the interface, and data received via the interface before they are written to the storage location.
摘要翻译：存储设备包括存储位置，耦合到存储位置的接口以及耦合到存储位置和接口的数据转换电路。该接口被配置为在存储设备和耦合到接口的外部电路之间进行数据交换。数据转换电路被配置为将数据从第一数据格式转换成第二数据格式。数据转换电路被配置为将从存储位置读取的数据中的至少一个转换到接口，以及在被写入存储位置之前经由接口接收到的数据。

3. 发明申请

US20090002383A1 MEMORY FOR PROVIDING A GRAPHIC CONTENT 有权
标题翻译：提供图形内容的记忆
公开(公告)号：US20090002383A1
公开(公告)日：2009-01-01
申请号：US11771834
申请日：2007-06-29
申请人： Christoph Bilger , Rex Kho , Achim Schramm , Martin Maier , Yann Zinzius , Armin Kohlhase
发明人： Christoph Bilger , Rex Kho , Achim Schramm , Martin Maier , Yann Zinzius , Armin Kohlhase
IPC分类号： G09G5/39
CPC分类号： G09G5/395 , G06T1/60
摘要： A memory device comprises a memory array and a processing device. The memory array is configured to store a graphic data set. The processing device is configured to initiate outputting of data of the graphic data set from the memory array and to combine the outputted data in response to a read request for providing a graphic content.
摘要翻译：存储器件包括存储器阵列和处理器件。存储器阵列被配置为存储图形数据集。处理装置被配置为响应于用于提供图形内容的读取请求，启动从存储器阵列输出图形数据集的数据并组合输出的数据。

4. 发明授权

US07415569B2 Memory including a write training block 有权
标题翻译：内存包括一个写入训练块
公开(公告)号：US07415569B2
公开(公告)日：2008-08-19
申请号：US11386360
申请日：2006-03-22
申请人： Stefan Dietrich , Rex Kho
发明人： Stefan Dietrich , Rex Kho
IPC分类号： G06F12/00
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter and a write training block. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for moving the FIFO output pointer based on data read from the FIFO cells.
摘要翻译：存储器包括多个先进先出（FIFO）单元，输出指针计数器和写入训练块。输出指针计数器用于切换FIFO单元格中FIFO输出指针的值。写入训练块用于根据从FIFO单元读取的数据产生用于移动FIFO输出指针的信息。

5. 发明授权

US07411862B2 Control signal training 有权
标题翻译：控制信号训练
公开(公告)号：US07411862B2
公开(公告)日：2008-08-12
申请号：US11560293
申请日：2006-11-15
申请人： Thomas Hein , Aaron John Nygren , Rex Kho
发明人： Thomas Hein , Aaron John Nygren , Rex Kho
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C7/22 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A control signal training system in an integrated circuit comprises a signal transmitting unit, the signal transmitting unit outputting control signals and sampling clock signals, the control signals and the sampling clock signals having a predetermined time phase with respect to each other, a signal receiving unit, the signal receiving unit latching control signals in relation to the sampling clock signals, and an evaluation unit connected to a reading unit and the signal transmitting unit, the evaluation unit determining concordance of the control signals outputted by the signal transmitting unit and the control signals read out by the reading unit from the signal receiving unit, the evaluation unit adapting the time phase between the control signals and the sampling clock signals step-by-step until concordance of the control signals outputted by the signal transmitting unit and the control signals read out the reading unit from the signal receiving unit is determined by the evaluation unit.
摘要翻译：集成电路中的控制信号训练系统包括信号发送单元，信号发送单元输出控制信号和采样时钟信号，控制信号和采样时钟信号相对于彼此具有预定的时间相位;信号接收单元信号接收单元相对于采样时钟信号锁存控制信号，以及连接到读取单元和信号发送单元的评估单元，评估单元确定由信号发送单元输出的控制信号和控制信号的一致性由读取单元从信号接收单元读出，评估单元逐步调整控制信号与采样时钟信号之间的时间相位，直到由信号发送单元输出的控制信号和读取的控制信号的一致从信号接收单元输出读取单元由评估确定单位。

6. 发明申请

US20050213417A1 Circuit arrangement for latency regulation 有权
标题翻译：延迟调节的电路布置
公开(公告)号：US20050213417A1
公开(公告)日：2005-09-29
申请号：US11069789
申请日：2005-03-01
申请人： Rex Kho
发明人： Rex Kho
IPC分类号： G11C7/22 , G11C8/00 , G11C11/4076
CPC分类号： G11C11/4096 , G11C7/1039 , G11C7/1066 , G11C7/1069 , G11C7/222 , G11C11/4076
摘要： One embodiment of the invention relates to a circuit arrangement for regulating a latency that is defined as a whole number n of periods T of a reference clock of frequency fc and is intended to elapse, as of a data transmission command, before the data which are to be transmitted from a data source appear at the end of the data path that is to be passed through and contains a chain of transmission elements having fixed delay times. The frequency fc may be set in a range from 1/Tmax to 1/Tmin, where Tmin is at least equal to τf/n and τf is equal to the sum of the fixed delay times in the data path. The data path is subdivided into n successive sections, each of which contains, at its input, a clock-controlled sampling element for accepting the data to be transmitted and has a propagation time that is considerably shorter than Tmin. The propagation time τn of the last section (Sn) is considerably greater than zero. The clock of the sampling elements is controlled using a version of the reference clock that has been delayed by T−τn.
摘要翻译：本发明的一个实施例涉及一种用于调节等待时间的电路装置，该等待时间被定义为频率f C c C的参考时钟的周期T的整数n，并且要从数据在要从数据源发送的数据出现在要通过的数据路径的末端并且包含具有固定延迟时间的传输元件链之前。频率f C c可以设定在1 / T max max到1 / T min min的范围内，其中T min min / SUB>至少等于τ1/ f，并且τ1等于数据路径中的固定延迟时间之和。数据路径被细分成n个连续的部分，每个连续的部分在其输入处包含一个时钟控制的采样元件，用于接收要传输的数据，并且具有比T分钟短的传播时间。最后一个部分（Sn）的传播时间τN n大大超过零。采样元件的时钟是使用延迟了T-τ的参考时钟的版本进行控制的。

7. 发明授权

US07620857B2 Controllable delay device 失效
标题翻译：可控延迟装置
公开(公告)号：US07620857B2
公开(公告)日：2009-11-17
申请号：US11382231
申请日：2006-05-08
申请人： Rex Kho
发明人： Rex Kho
IPC分类号： G06K5/04 , G11B5/00 , G11B20/20 , H03L7/06 , H03L7/00 , H03H11/26 , H04B3/46 , H04B17/00 , H04Q1/20 , H04L7/00 , H04L25/00 , H04L25/40 , H03D3/24 , G04F1/00 , G04F3/00 , G04F5/00 , G04F7/00 , G04F8/00 , G04F10/00 , G04G5/00 , G04G7/00 , G04G15/00 , G06F9/45
CPC分类号： H03K5/131 , H03K2005/00058
摘要： Two delay chains having in each case n series-connected unidirectional delay elements are provided for controllably delaying electrical signals between a circuit input and at least one circuit output. Each delay element is an active circuit with a fixed transit time. The input of the first delay element of the first chain is connected to the circuit input and the output of each delay element of the first delay chain is selectively connectable to the input of the (n−i+1)th delay element of the second delay chain via a respectively associated switch of a first group of switches, wherein i=1 . . . n is the ordinal number of the delay elements of the first delay chain. The output of the last delay element of the second chain is connected as a circuit output.
摘要翻译：在每种情况下，提供两个延迟链，其中n个串联连接的单向延迟元件用于可控地延迟电路输入和至少一个电路输出之间的电信号。每个延迟元件是具有固定通行时间的有源电路。第一链的第一延迟元件的输入连接到电路输入，第一延迟链的每个延迟元件的输出可选择地连接到第二延迟链的第（n-1）个延迟元件的输入端延迟链通过第一组开关的分别关联的开关，其中i = 1。。。 n是第一延迟链的延迟元件的序数。第二链的最后一个延迟元件的输出作为电路输出连接。

8. 发明申请

US20090125984A1 SYSTEM AND METHOD FOR ESTABLISHING DATA CONNECTIONS BETWEEN ELECTRONIC DEVICES 失效
标题翻译：用于建立电子设备之间的数据连接的系统和方法
公开(公告)号：US20090125984A1
公开(公告)日：2009-05-14
申请号：US11939892
申请日：2007-11-14
申请人： Christoph Bilger , Rex Kho , Achim Schramm , Martin Maier , Yann Zinzius , Armin Kohlhase
发明人： Christoph Bilger , Rex Kho , Achim Schramm , Martin Maier , Yann Zinzius , Armin Kohlhase
IPC分类号： H04L9/32
CPC分类号： H04L9/321 , H04L2209/805
摘要： A system and method is disclosed, including establishing of data connections between electronic devices. One embodiment provides a method for establishing a data connection between a first and a second electronic device, wherein establishing the data connection is authorized by executing at least one action with at least one physical tool.
摘要翻译：公开了一种系统和方法，包括建立电子设备之间的数据连接。一个实施例提供了一种用于在第一和第二电子设备之间建立数据连接的方法，其中通过用至少一个物理工具执行至少一个动作来建立数据连接。

9. 发明授权

US07457913B2 Finding a data pattern in a memory 有权
标题翻译：在内存中查找数据模式
公开(公告)号：US07457913B2
公开(公告)日：2008-11-25
申请号：US11386176
申请日：2006-03-22
申请人： Stefan Dietrich , Rex Kho
发明人： Stefan Dietrich , Rex Kho
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G11C7/1006 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C15/04
摘要： A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a multiplexer. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for shifting the FIFO output pointer based on data read from the FIFO cells. The multiplexer is for receiving the value of the FIFO output pointer from the output pointer counter. The multiplexer is also for receiving the multiplexing information for shifting the FIFO output pointer. The multiplexer is further for shifting the value of the FIFO output pointer based on the multiplexing information.
摘要翻译：存储器包括多个先进先出（FIFO）单元，输出指针计数器，写入训练块和多路复用器。输出指针计数器用于切换FIFO单元格中FIFO输出指针的值。写入训练块用于根据从FIFO单元读取的数据产生用于移位FIFO输出指针的信息。多路复用器用于从输出指针计数器接收FIFO输出指针的值。复用器还用于接收用于移位FIFO输出指针的复用信息。复用器还用于基于复用信息来移位FIFO输出指针的值。

10. 发明申请

US20080112255A1 TRAINING OF SIGNAL TRANSFER CHANNELS BETWEEN MEMORY CONTROLLER AND MEMORY DEVICE 审中-公开
标题翻译：记忆控制器与存储器件之间信号传输通道的训练
公开(公告)号：US20080112255A1
公开(公告)日：2008-05-15
申请号：US11560302
申请日：2006-11-15
申请人： Aaron John Nygren , Thomas Hein , Rex Kho
发明人： Aaron John Nygren , Thomas Hein , Rex Kho
IPC分类号： G11C8/00
CPC分类号： G11C29/02 , G11C5/04 , G11C29/025 , G11C29/50012
摘要： Apparatus and method of training a data transfer channel between a memory controller and a memory device connected to each other via a data signal transfer channel and an address signal transfer channel. The method comprises reading test data from a latching circuit connected to both an address signal input and a data or control signal output of the memory device or from a read only memory in the memory device, transferring a read signal representing the test data via the data signal transfer channel, detecting data from the read signal with a delay relative to a read clock signal; repeating the transferring, detecting steps, each time detecting the data at a different value of the delay; selecting a value of the delay, preferably a value at which the detected data equal the test data; and setting the delay to the selected value.
摘要翻译：通过数据信号传送通道和地址信号传送通道在存储器控制器和连接到彼此的存储器件之间训练数据传送通道的装置和方法。该方法包括从连接到存储器件的地址信号输入和数据或控制信号输出的存储电路或从存储器件中的只读存储器读取测试数据，经由数据传送表示测试数据的读取信号信号传输通道，相对于读取时钟信号以相对于读取时钟信号的延迟来检测来自读取信号的数据; 每次以不同的延迟值检测数据，重复传送，检测步骤; 选择延迟的值，优选地是检测数据等于测试数据的值; 并将延迟设置为所选值。

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