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1. 发明申请

US20130135954A1 MEMORY CELL ARRAY LATCHUP PREVENTION 有权
标题翻译：存储单元阵列预防
公开(公告)号：US20130135954A1
公开(公告)日：2013-05-30
申请号：US13280937
申请日：2011-10-25
申请人： Ravindra M. Kapre , Shahin Sharifzadeh
发明人： Ravindra M. Kapre , Shahin Sharifzadeh
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14 , H01L27/0921 , H02H9/025
摘要： A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.
摘要翻译：提供了一种互补场效应（CMOS）电路，其包括沿该电路的电源总线或接地总线布置的限流装置。限流器件被配置为防止CMOS电路的锁存。更具体地，限流装置被配置为保持寄生pnpn二极管结构的结为反向偏置。还提供了一种方法，其包括产生布置在第一CMOS电路内的pnpn二极管的电压 - 电压曲线图，该第一CMOS电路不存在沿着该电路的电力总线布置的限流装置。此外，该方法包括从电流 - 电压图确定保持电流电平，并且限制限流器件沿着包括与第一CMOS电路相似的设计规范的第二CMOS电路的电源总线放置，使得通过第二CMOS电路不超过保持电流电平。

2. 发明授权

US07773442B2 Memory cell array latchup prevention 有权
标题翻译：存储单元阵列闭锁预防
公开(公告)号：US07773442B2
公开(公告)日：2010-08-10
申请号：US10877313
申请日：2004-06-25
申请人： Ravindra M. Kapre , Shahin Sharifzadeh
发明人： Ravindra M. Kapre , Shahin Sharifzadeh
IPC分类号： G11C7/02
CPC分类号： G11C11/417 , G11C5/14 , H01L27/0921 , H02H9/025
摘要： A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.
摘要翻译：提供了一种互补场效应（CMOS）电路，其包括沿该电路的电源总线或接地总线布置的限流装置。限流器件被配置为防止CMOS电路的锁存。更具体地，限流装置被配置为保持寄生pnpn二极管结构的结为反向偏置。还提供了一种方法，其包括产生布置在第一CMOS电路内的pnpn二极管的电压 - 电压曲线图，该第一CMOS电路不存在沿着该电路的电力总线布置的限流装置。此外，该方法包括从电流 - 电压图确定保持电流电平，并且限制限流器件沿着包括与第一CMOS电路相似的设计规范的第二CMOS电路的电源总线放置，使得通过第二CMOS电路不超过保持电流电平。

3. 发明授权

US06747318B1 Buried channel devices and a process for their fabrication simultaneously with surface channel devices to produce transistors and capacitors with multiple electrical gate oxides 有权
标题翻译：掩埋通道器件及其与表面沟道器件同时制造的工艺，以生产具有多个电栅极氧化物的晶体管和电容器
公开(公告)号：US06747318B1
公开(公告)日：2004-06-08
申请号：US10020304
申请日：2001-12-13
申请人： Ravindra M. Kapre , Tommy Hsiao , Yanhua Wang , Kyungjin Min
发明人： Ravindra M. Kapre , Tommy Hsiao , Yanhua Wang , Kyungjin Min
IPC分类号： H01L2994
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823892 , H01L29/7838 , H01L29/94
摘要： A method for fabricating buried channel NMOS devices and the devices themselves are disclosed. These buried channel NMOS devices are fabricated with a p-type substrate, an n-type implant in the top portion (approximately 400 to 1000 Å deep) of the substrate, and an insulating gate dielectric above the n-type implant. An n-type or p-type doped polysilicon gate electrode is formed on top of the insulating gate dielectric. The n-type implant region is doped in such a way that it is depleted of charge carriers when the device's gate electrode is at the same potential as the well (zero bias). When the gate electrode is biased +Ve with respect to the device's well substrate a conducting channel of mobile electrons is formed in a portion of the buried layer. This type of biasing is known as inversion bias since the charge carriers are of the opposite type than the p-well. Under inversion bias, the buried channel silicon region is partially depleted of charge carriers, which effectively adds to the thickness of the gate dielectric layer. A capacitor or transistor fabricated according to this buried channel teaching behaves in a manner electrically equivalent to a capacitor or transistor fabricated with a thicker dielectric. PMOS transistors and capacitors can be constructed according to the present invention in a manner similar to that described for NMOS transistors and capacitors by substituting n-type doping for p-type and visa versa. This leads to the fabrication of CMOS devices with multiple effective dielectric thicknesses on the same substrate.
摘要翻译：公开了一种用于制造掩埋沟道NMOS器件和器件本身的方法。这些掩埋沟道NMOS器件由p型衬底，衬底的顶部（约400至1000深）中的n型注入器以及n型注入器之上的绝缘栅极电介质制成。在绝缘栅极电介质的顶部上形成n型或p型掺杂多晶硅栅电极。掺杂n型注入区的方式是当器件的栅电极处于与阱相同的电位（零偏压）时，其耗尽电荷载流子。当栅电极相对于器件的阱衬底偏置+ Ve时，移动电子的导电沟道形成在掩埋层的一部分中。这种偏置称为反向偏置，因为电荷载体与p阱相反。在反向偏置下，掩埋沟道硅区域部分耗尽电荷载流子，这有效地增加了栅极介电层的厚度。根据该掩埋通道示教制造的电容器或晶体管以与电介质较厚的电容器或晶体管电气等效的方式起作用。根据本发明，PMOS晶体管和电容器可以以类似于对NMOS晶体管和电容器描述的方式构造，通过用n型掺杂代替p型，反之亦然。这导致在同一衬底上制造具有多个有效介电厚度的CMOS器件。

4. 发明授权

US06521549B1 METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT 有权
标题翻译：在混合集成电路的某些晶体管中减少硅氧烷栅绝缘体厚度的方法，以获得具有混合电路的其他晶体管的栅绝缘体厚度增加的差异
公开(公告)号：US06521549B1
公开(公告)日：2003-02-18
申请号：US09724225
申请日：2000-11-28
申请人： Arvind Kamath , Rajiv Patel , Ravindra M. Kapre
发明人： Arvind Kamath , Rajiv Patel , Ravindra M. Kapre
IPC分类号： H01L21469
CPC分类号： H01L21/823462
摘要： A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.
摘要翻译：数字开关晶体管的相对薄的栅极绝缘体由氮氧化硅层形成，其最初通过在硅衬底中注入氮原子并氧化氮和硅而形成。已经发现，作为氧氮化硅层的一部分形成二氧化硅的外层。从氮氧化硅层中除去二氧化硅外层留下基本上只有氮氧化硅的薄剩余层作为栅极绝缘体。例如，大约15-21埃的较薄的栅极绝缘体可以由例如60埃的生长厚度形成。用于数字和模拟晶体管的栅极绝缘体可以同时形成，通过使用常规氮注入技术，可以获得更大的厚度差。

5. 发明授权

US08493804B2 Memory cell array latchup prevention 有权
标题翻译：存储单元阵列闭锁预防
公开(公告)号：US08493804B2
公开(公告)日：2013-07-23
申请号：US13280937
申请日：2011-10-25
申请人： Ravindra M. Kapre , Shahin Sharifzadeh
发明人： Ravindra M. Kapre , Shahin Sharifzadeh
IPC分类号： G11C7/02
CPC分类号： G11C11/417 , G11C5/14 , H01L27/0921 , H02H9/025
摘要： An embodiment includes configuring a current-limiting device to place along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus.
摘要翻译：一个实施例包括配置限流装置沿着电源总线放置以限制电流通过耦合到电源总线的第一互补金属氧化物半导体（CMOS）电路，使得电流不超过触发电流电平在连接到电源总线的第二CMOS电路中的pnpn二极管。

6. 发明授权

US06656805B2 METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT 失效
公开(公告)号：US06656805B2
公开(公告)日：2003-12-02
申请号：US10304631
申请日：2002-11-26
申请人： Arvind Kamath , Rajiv Patel , Ravindra M. Kapre
发明人： Arvind Kamath , Rajiv Patel , Ravindra M. Kapre
IPC分类号： H01L21336
CPC分类号： H01L21/823462
摘要： A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.

7. 发明授权

US08252640B1 Polycrystalline silicon activation RTA 有权
标题翻译：多晶硅活化RTA
公开(公告)号：US08252640B1
公开(公告)日：2012-08-28
申请号：US11555905
申请日：2006-11-02
申请人： Ravindra M. Kapre , Sethuraman Lakshminarayanan
发明人： Ravindra M. Kapre , Sethuraman Lakshminarayanan
IPC分类号： H01L21/336
CPC分类号： H01L21/28247 , H01L27/1104 , H01L29/66575 , H01L29/78
摘要： A method of forming a semiconductor structure includes rapid thermal annealing of a gate stack on a semiconductor substrate at a temperature of at least 950° C., followed by forming source/drain regions in the semiconductor substrate.
摘要翻译：形成半导体结构的方法包括在至少950℃的温度下半导体衬底上的栅极堆叠的快速热退火，随后在半导体衬底中形成源极/漏极区域。

8. 发明授权

US08045410B2 Memory cell array 有权
标题翻译：存储单元阵列
公开(公告)号：US08045410B2
公开(公告)日：2011-10-25
申请号：US12434084
申请日：2009-05-01
申请人： Ravindra M. Kapre , Shahin Sharifzadeh
发明人： Ravindra M. Kapre , Shahin Sharifzadeh
IPC分类号： G11C7/02
CPC分类号： G11C11/417 , G11C5/14 , H01L27/0921 , H02H9/025
摘要： A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.
摘要翻译：提供了一种互补场效应（CMOS）电路，其包括沿着电源总线或电路的接地总线布置的限流装置。限流装置被配置为防止CMOS电路的锁存。更具体地，限流装置被配置为保持寄生pnpn二极管结构的结为反向偏置。还提供了一种方法，其包括产生布置在第一CMOS电路内的pnpn二极管的电压 - 电压曲线图，该第一CMOS电路不存在沿着该电路的电力总线布置的限流装置。此外，该方法包括从电流 - 电压图确定保持电流电平，并且限制限流器件沿着包括与第一CMOS电路相似的设计规范的第二CMOS电路的电源总线放置，使得通过第二CMOS电路不超过保持电流电平。

9. 发明申请

US20090213677A1 Memory Cell Array 有权
标题翻译：存储单元阵列
公开(公告)号：US20090213677A1
公开(公告)日：2009-08-27
申请号：US12434084
申请日：2009-05-01
申请人： Ravindra M. Kapre , Shahin Sharifzadeh
发明人： Ravindra M. Kapre , Shahin Sharifzadeh
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14 , H01L27/0921 , H02H9/025
摘要： A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.
摘要翻译：提供了一种互补场效应（CMOS）电路，其包括沿着电源总线或电路的接地总线布置的限流装置。限流装置被配置为防止CMOS电路的锁存。更具体地，限流装置被配置为保持寄生pnpn二极管结构的结为反向偏置。还提供了一种方法，其包括产生布置在第一CMOS电路内的pnpn二极管的电压 - 电压曲线图，该第一CMOS电路不存在沿着该电路的电力总线布置的限流装置。此外，该方法包括从电流 - 电压图确定保持电流电平，并且限制限流器件沿着包括与第一CMOS电路相似的设计规范的第二CMOS电路的电源总线放置，使得通过第二CMOS电路不超过保持电流电平。

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