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1. 发明授权

US06563349B2 Multiplexor generating a glitch free output when selecting from multiple clock signals 有权
标题翻译：多路复用器从多个时钟信号中选择时产生无毛刺的输出
公开(公告)号：US06563349B2
公开(公告)日：2003-05-13
申请号：US09891541
申请日：2001-06-27
申请人： Vinod Menezes , Rajith Kumar Mavila
发明人： Vinod Menezes , Rajith Kumar Mavila
IPC分类号： H03K1700
CPC分类号： G06F1/08
摘要： A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the faster clock signal. The sleep signal is further synchronized with a negative edge of the slower clock signal and provided to an AND gate gating the slower clock signal based on the value of a select signal formed by the synchronized sleep signal. The slower clock signal is delayed by a number of faster clock cycles equal to the time taken by the select signal to be received at the AND gate after the sleep signal is synchronized to the slower clock signal. In an alternative embodiment, a signal control block ensures that the 0 to 1 transition on one of the select signals follows the 1 to 0 transition on another select signal when the value of the sleep signal changes. In addition, each select signal is synchronized with a negative edge of the corresponding clock signal selected.
摘要翻译：多路复用器产生无毛刺输出。较慢的时钟信号和睡眠时钟信号分别与较快时钟信号的正和负边沿同步。休眠信号进一步与较慢时钟信号的下降沿同步，并提供给基于由同步睡眠信号形成的选择信号的值门控较慢时钟信号的“与”门。较慢的时钟信号被延迟了等于在睡眠信号与较慢时钟信号同步之后在与门接收的选择信号所花费的时间的更快的时钟周期。在替代实施例中，当睡眠信号的值改变时，信号控制块确保在其中一个选择信号上的0至1转换在另一选择信号上的1至0转换之后。此外，每个选择信号与所选择的相应时钟信号的下降沿同步。

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