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1. 发明申请

US20100255991A1 PLANT CRYOPROTECTANT COMPOSITIONS AND METHODS OF USE 有权
标题翻译：植物蛋白质组合物及其使用方法
公开(公告)号：US20100255991A1
公开(公告)日：2010-10-07
申请号：US12664968
申请日：2008-06-17
申请人： David A. Francko , Kenneth G. Wilson , Quinn Li , Maria Alejandra Equiza
发明人： David A. Francko , Kenneth G. Wilson , Quinn Li , Maria Alejandra Equiza
IPC分类号： A01N59/00
CPC分类号： A01G13/00 , A01N3/00 , A01N31/02
摘要： The present disclosure relates to cryoprotection of plants. The compositions and methods disclosed herein provide a means for protecting plants from frost or freeze damage or death due to sudden exposure to low temperature conditions. The present disclosure further relates to methods for providing cryoprotection to plants.
摘要翻译：本公开涉及植物的冷冻保护。本文公开的组合物和方法提供了用于保护植物免受霜冻或由于突然暴露于低温条件而导致的冻结损伤或死亡的手段。本公开还涉及向植物提供冷冻保护的方法。

2. 发明申请

US20080159377A1 HIGH PERFORMANCE EQUALIZER WITH ENHANCED DFE HAVING REDUCED COMPLEXITY 审中-公开
标题翻译：高性能均衡器与增强的DFE具有降低的复杂性
公开(公告)号：US20080159377A1
公开(公告)日：2008-07-03
申请号：US12043517
申请日：2008-03-06
申请人： Steve A. Allpress , Quinn Li
发明人： Steve A. Allpress , Quinn Li
IPC分类号： G06F17/10 , H03H7/30
CPC分类号： H04L25/03261 , H04L25/03057 , H04L25/03076 , H04L25/03146 , H04L25/03171 , H04L2025/03401 , H04L2025/0349 , H04L2025/0356 , H04L2025/03796
摘要： An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1
摘要翻译：（1）将判决反馈均衡器（DFE）与最大后缀（MAP）均衡器（或最大似然序列估计器，MLSE）（2）的优点相结合的均衡器的装置和方法（2）执行均衡基于信道是最小相位或最大相位的时间前向或时间反转方式来提供具有比全状态MAP设备显着更低的复杂度的均衡设备，但仍然提供比常规DFE更好的性能。均衡器架构包括两个类似DFE的结构，其次是MAP均衡器。第一个DFE形成暂定的符号决定。此后使用第二DFE来截断对于L1 L1符号的期望存储器的信道响应，其小于信道的L个符号的总延迟扩展。 MAP均衡器在具有L 1 1符号（其中L 1> L =）的存储器的信道上操作，因此均衡器的总体复杂度显着降低。

3. 发明授权

US07151796B2 High performance equalizer with enhanced DFE having reduced complexity 失效
标题翻译：具有增强型DFE的高性能均衡器具有降低的复杂性
公开(公告)号：US07151796B2
公开(公告)日：2006-12-19
申请号：US09946648
申请日：2001-09-04
申请人： Steve A. Allpress , Quinn Li
发明人： Steve A. Allpress , Quinn Li
IPC分类号： G06F17/10 , H03H7/30
CPC分类号： H04L25/03261 , H04L25/03057 , H04L25/03076 , H04L25/03146 , H04L25/03171 , H04L2025/03401 , H04L2025/0349 , H04L2025/0356 , H04L2025/03796
摘要： An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1
摘要翻译：（1）将判决反馈均衡器（DFE）与最大后缀（MAP）均衡器（或最大似然序列估计器，MLSE）（2）的优点相结合的均衡器的装置和方法（2）执行均衡基于信道是最小相位或最大相位的时间前向或时间反转方式来提供具有比全状态MAP设备显着更低的复杂度的均衡设备，但仍然提供比常规DFE更好的性能。均衡器架构包括两个类似DFE的结构，其次是MAP均衡器。第一个DFE形成暂定的符号决定。此后使用第二DFE来截断对于L1 L1符号的期望存储器的信道响应，其小于信道的L个符号的总延迟扩展。 MAP均衡器在具有L 1 1符号（其中L 1> L =）的存储器的信道上操作，因此均衡器的总体复杂度显着降低。

4. 发明申请

US20060120446A1 Decision feedback equalizer for minimum and maximum phase channels 有权
公开(公告)号：US20060120446A1
公开(公告)日：2006-06-08
申请号：US11344406
申请日：2006-01-31
申请人： Steve Allpress , Quinn Li
发明人： Steve Allpress , Quinn Li
IPC分类号： H03H7/30 , H04B1/10
CPC分类号： H04L25/03261 , H04L25/03057 , H04L25/03076 , H04L2025/03401 , H04L2025/0356 , H04L2025/03796
摘要： This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For minimum-phase channels, the equalization is performed in a time-forward manner. For maximum-phase channels, the equalization is performed in a time-reversed manner. More specifically, for maximum-phase channels, the filter coefficients are computed based on the channel estimates reversed in time, and the filtering and equalization operations are performed with the received block of symbols in a time-reversed order. In the context of this invention, the term “minimum-phase channel” implies that the energy of the leading part of the channel profile is greater than the energy of the trailing part. The term “maximum-phase channel” implies that the energy of the leading part of the channel profile is less than the energy of the trailing part.

5. 发明授权

US07012957B2 High performance equalizer having reduced complexity 有权
标题翻译：高性能均衡器具有降低的复杂性
公开(公告)号：US07012957B2
公开(公告)日：2006-03-14
申请号：US09941300
申请日：2001-08-27
申请人： Stephen Allpress , Quinn Li
发明人： Stephen Allpress , Quinn Li
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03171 , H04L25/03057 , H04L25/03076 , H04L25/03146 , H04L25/03261 , H04L2025/03401 , H04L2025/0349 , H04L2025/0356 , H04L2025/03796
摘要： An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1
摘要翻译：一种用于实现均衡器的装置和方法，其将判决反馈均衡器（DFE）与最大似然序列估计器（MLSE）的最大似然序列估计器（MLSE）的优点相结合，以提供具有显着更低复杂度的均衡器件而不是全状态MAP设备，但仍然提供比传统DFE更好的性能。均衡器架构包括两个类似DFE的结构，其次是MAP均衡器。第一个DFE形成暂定的符号决定。此后使用第二DFE来截断对于L1 L1符号的期望存储器的信道响应，其小于信道的L个符号的总延迟扩展。 MAP均衡器在具有L 1 1符号（其中L 1> L =）的存储器的信道上操作，因此均衡器的总体复杂度显着降低。

6. 发明授权

US06590873B1 Channel structure for forward link power control 有权
标题翻译：前向链路功率控制的通道结构
公开(公告)号：US06590873B1
公开(公告)日：2003-07-08
申请号：US09245204
申请日：1999-02-05
申请人： Quinn Li , Martin Howard Meyers , John Minkoff , Xiao Cheng Wu
发明人： Quinn Li , Martin Howard Meyers , John Minkoff , Xiao Cheng Wu
IPC分类号： H04B7185
CPC分类号： H04W52/58
摘要： The invention is a method for controlling power on multiple forward link communication channels by using multiple power control sub-channels, wherein each power control sub-channel is associated with a forward link communication channel to be power controlled. A fundamental power control sub-channel and a supplemental power control sub-channel are time multiplexed onto a reverse pilot channel. Transmitted over the fundamental power control sub-channel is a fundamental power control bit for indicating to a base station to increase or decrease its transmission power over a corresponding forward fundamental channel. Transmitted over the supplemental power control sub-channel is a supplemental power control bit for indicating to a base station to increase or decrease its transmission power over a corresponding forward supplemental channel. The pilot sub-channels are preferably separated by the fundamental and supplemental power control sub-channels for time diversity purposes.
摘要翻译：本发明是一种通过使用多个功率控制子信道来控制多个前向链路通信信道上的功率的方法，其中每个功率控制子信道与要被功率控制的前向链路通信信道相关联。基本功率控制子信道和补充功率控制子信道被时分复用到反向导频信道上。通过基本功率控制子信道发送的是用于向基站指示在相应的前向基本信道上增加或减少其发送功率的基本功率控制位。通过补充功率控制子信道传输的补充功率控制位用于向基站指示在相应的前向补充信道上增加或减少其发射功率。导频子信道优选地由用于时间分集目的的基本和补充功率控制子信道分离。

7. 发明授权

US06535723B1 Method of power control for a wireless communication system having multiple information rates 有权
标题翻译：具有多种信息速率的无线通信系统的功率控制方法
公开(公告)号：US06535723B1
公开(公告)日：2003-03-18
申请号：US09267998
申请日：1999-03-15
申请人： Frances Jiang , Raafat Edward Kamel , Quinn Li , Alexandro Federico Salvarani , Carl Francis Weaver
发明人： Frances Jiang , Raafat Edward Kamel , Quinn Li , Alexandro Federico Salvarani , Carl Francis Weaver
IPC分类号： H04B106
CPC分类号： H04W52/265 , H04W52/12 , H04W52/241 , H04W52/267 , H04W52/36 , H04W52/40
摘要： A method of controlling the power in a wireless communication system. In one embodiment of the invention, a base station determines the information rate of a signal to be transmitted to a mobile station, and obtains the variable power control scaling factor based on this information rate. The base station then transmits the variable power control scaling factor to the mobile station. The mobile station determines a target signal quality measurement for a received signal from the base station, such as a target Eb/N0, and scales the target Eb/N0 by the variable power control scaling factor. The mobile station also obtains an information rate scaling factor based on the information rate of the received signal, and further scales the target Eb/N0 by this information rate scaling factor. The mobile station then compares the target Eb/N0 to a measured Eb/N0 of the received signal. An increase in power of the received signal is requested when the measured Eb/N0 of the received signal is smaller than the scaled Eb/N0. A decrease in power of the received signal is requested when the measured Eb/N0 of the received signal is larger than the scaled Eb/N0. Providing the variable power control scaling factor to the mobile station allows frames having an information rate lower than the full rate to be transmitted at a power even lower than the power of a frame having an information rate equal to the full rate times the information scaling factor.
摘要翻译：一种在无线通信系统中控制功率的方法。在本发明的一个实施例中，基站确定要发送到移动台的信号的信息速率，并且基于该信息速率获得可变功率控制缩放因子。然后，基站向移动台发送可变功率控制缩放因子。移动台确定来自诸如目标Eb / N0的基站的接收信号的目标信号质量测量，并且通过可变功率控制缩放因子对目标Eb / N0进行缩放。移动站还根据接收信号的信息速率获得信息速率缩放因子，并且通过该信息速率缩放因子进一步缩放目标Eb / N0。然后，移动台将目标Eb / N0与接收信号的测量Eb / N0进行比较。当所测量的接收信号的Eb / N0小于缩放的Eb / N0时，请求接收信号功率的增加。当所测量的接收信号的Eb / N0大于缩放的Eb / N0时，请求接收信号功率的降低。向移动台提供可变功率控制缩放因子允许具有低于全速率的信息速率的帧以甚至低于具有等于全速率的信息速率的帧的功率乘以信息缩放因子的功率发送。

8. 发明授权

US06392988B1 Transmitter architecture employing space time spreading and orthogonal transmit diversity techniques 有权
标题翻译：采用时空扩展和正交发射分集技术的发射机架构
公开(公告)号：US06392988B1
公开(公告)日：2002-05-21
申请号：US09394172
申请日：1999-09-13
申请人： Stephen Alan Allpress , R. Michael Buehrer , Quinn Li , Nallepilli S. Ramesh , Robert Atmaram Soni
发明人： Stephen Alan Allpress , R. Michael Buehrer , Quinn Li , Nallepilli S. Ramesh , Robert Atmaram Soni
IPC分类号： H04J1100
CPC分类号： H04L1/0618
摘要： Disclosed is a common transmitter architecture having incorporated both open loop transmit diversity schemes using a plurality of binary switches. Employment of binary switches allows for the sharing of certain components whether the transmitter is utilizing a orthogonal transmit diversity (OTD) scheme or a space time spreading (STS) scheme. Accordingly, the number of components in the transmitter is minimized and the complexity of the transmitter is simple enough to be implemented into a single application specific integrated chip.
摘要翻译：公开了一种共同的发射机架构，其结合了使用多个二进制交换机的开环发射分集方案。二进制交换机的使用允许某些组件的共享，无论发射机是利用正交发射分集（OTD）方案还是空间时间扩展（STS）方案。因此，发射机中的组件数量被最小化，并且发射机的复杂性足够简单以被实现到单个专用集成芯片中。

9. 发明授权

US07656943B2 High performance equalizer having reduced complexity 有权
标题翻译：高性能均衡器具有降低的复杂性
公开(公告)号：US07656943B2
公开(公告)日：2010-02-02
申请号：US11376002
申请日：2006-03-14
申请人： Stephen Allpress , Quinn Li
发明人： Stephen Allpress , Quinn Li
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03171 , H04L25/03057 , H04L25/03076 , H04L25/03146 , H04L25/03261 , H04L2025/03401 , H04L2025/0349 , H04L2025/0356 , H04L2025/03796
摘要： An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1
摘要翻译：一种用于实现均衡器的装置和方法，其将判决反馈均衡器（DFE）与最大似然序列估计器（MLSE）的最大似然序列估计器（MLSE）的优点相结合，以提供具有显着更低复杂度的均衡器件而不是全状态MAP设备，但仍然提供比传统DFE更好的性能。均衡器架构包括两个类似DFE的结构，其次是MAP均衡器。第一个DFE形成暂定的符号决定。此后使用第二DFE来截断对L1符号的期望存储器的信道响应，其小于信道的L个符号的总延迟扩展。 MAP均衡器在具有L1符号（其中L1 <= L）的存储器的信道上操作，因此均衡器的总体复杂度显着降低。

10. 发明授权

US07006563B2 Decision feedback equalizer for minimum and maximum phase channels 有权
公开(公告)号：US07006563B2
公开(公告)日：2006-02-28
申请号：US09941027
申请日：2001-08-27
申请人： Steve A. Allpress , Quinn Li
发明人： Steve A. Allpress , Quinn Li
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03261 , H04L25/03057 , H04L25/03076 , H04L2025/03401 , H04L2025/0356 , H04L2025/03796
摘要： This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For minimum-phase channels, the equalization is performed in a time-forward manner. For maximum-phase channels, the equalization is performed in a time-reversed manner. More specifically, for maximum-phase channels, the filter coefficients are computed based on the channel estimates reversed in time, and the filtering and equalization operations are performed with the received block of symbols in a time-reversed order. In the context of this invention, the term “minimum-phase channel” implies that the energy of the leading part of the channel profile is greater than the energy of the trailing part. The term “maximum-phase channel” implies that the energy of the leading part of the channel profile is less than the energy of the trailing part.

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