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1. 发明申请

US20110149981A1 DEADLOCK PREVENTION IN DIRECT NETWORKS OF ARBITRARY TOPOLOGY 有权
标题翻译：直接网络中的死亡预防措施
公开(公告)号：US20110149981A1
公开(公告)日：2011-06-23
申请号：US12643280
申请日：2009-12-21
申请人： Peter Michael Klausler
发明人： Peter Michael Klausler
IPC分类号： H04L12/56
CPC分类号： H04L47/12 , G06F15/17312 , G06F15/17381 , H04L45/06 , H04L45/18 , H04L45/60 , H04L49/253
摘要： Aspects of the invention pertain to routing packets in a computer system while avoiding deadlock. A turn rule is set according to unique identifiers associated with switches in the system. Numeric values of switches in possible turns are compared to determine whether a turn is permissible. The rule applies to all nodes in the system. The rule may be violated when using virtual channels. Here, a violation is permissible when using monotonically increasing virtual channel numbers or monotonically decreasing virtual channel numbers. Alternatively, the violations of the turn rule may be allowed if they force a packet to change to a later virtual channel in some fixed ordering of virtual channels. Deadlock can thus be avoided in many different types of architectures, including mesh, torus, butterfly and flattened butterfly configurations.
摘要翻译：本发明的方面涉及在计算机系统中路由分组，同时避免死锁。根据与系统中的开关相关联的唯一标识符设置转弯规则。比较可能转弯中开关的数值，以确定转弯是否允许。该规则适用于系统中的所有节点。使用虚拟通道时可能会违反规则。这里，当使用单调递增的虚拟通道号或单调递减虚拟通道号时，允许违规。或者，如果在某些固定的虚拟通道排序中强制分组改变为稍后的虚拟通道，则可能允许违反转弯规则。因此，可以在许多不同类型的架构中避免死锁，包括网格，环面，蝴蝶和扁平蝶形配置。

2. 发明授权

US08139490B2 Deadlock prevention in direct networks of arbitrary topology 有权
标题翻译：任意拓扑直接网络中的死锁预防
公开(公告)号：US08139490B2
公开(公告)日：2012-03-20
申请号：US12643280
申请日：2009-12-21
申请人： Peter Michael Klausler
发明人： Peter Michael Klausler
IPC分类号： H04L1/00 , H04L12/26 , H04L12/28 , H04L12/56
CPC分类号： H04L47/12 , G06F15/17312 , G06F15/17381 , H04L45/06 , H04L45/18 , H04L45/60 , H04L49/253
摘要： Aspects of the invention pertain to routing packets in a computer system while avoiding deadlock. A turn rule is set according to unique identifiers associated with switches in the system. Numeric values of switches in possible turns are compared to determine whether a turn is permissible. The rule applies to all nodes in the system. The rule may be violated when using virtual channels. Here, a violation is permissible when using monotonically increasing virtual channel numbers or monotonically decreasing virtual channel numbers. Alternatively, the violations of the turn rule may be allowed if they force a packet to change to a later virtual channel in some fixed ordering of virtual channels. Deadlock can thus be avoided in many different types of architectures, including mesh, torus, butterfly and flattened butterfly configurations.
摘要翻译：本发明的方面涉及在计算机系统中路由分组，同时避免死锁。根据与系统中的开关相关联的唯一标识符设置转弯规则。比较可能转弯中开关的数值，以确定转弯是否允许。该规则适用于系统中的所有节点。使用虚拟通道时可能会违反规则。这里，当使用单调递增的虚拟通道号或单调递减虚拟通道号时，允许违规。或者，如果在某些固定的虚拟通道排序中强制分组改变为稍后的虚拟通道，则可能允许违反转弯规则。因此，可以在许多不同类型的架构中避免死锁，包括网格，环面，蝴蝶和扁平蝶形配置。

3. 发明授权

US08601297B1 Systems and methods for energy proportional multiprocessor networks 有权
标题翻译：能量比例多处理器网络的系统和方法
公开(公告)号：US08601297B1
公开(公告)日：2013-12-03
申请号：US12818580
申请日：2010-06-18
申请人： Dennis C. Abts , Peter Michael Klausler , Hong Liu , Michael Marty , Philip Wells
发明人： Dennis C. Abts , Peter Michael Klausler , Hong Liu , Michael Marty , Philip Wells
IPC分类号： G06F1/32
CPC分类号： G06F1/3253 , H04L41/0833 , H04L43/0882 , H04L69/14 , Y02D10/151 , Y02D50/30
摘要： Energy proportional solutions are provided for computer networks such as datacenters. Congestion sensing heuristics are used to adaptively route traffic across links. Traffic intensity is sensed and links are dynamically activated as they are needed. As the offered load is decreased, the lower channel utilization is sensed and the link speed is reduced to save power. Flattened butterfly topologies can be used in a further power saving approach. Switch mechanisms are exploit the topology's capabilities by reconfiguring link speeds on-the-fly to match bandwidth and power with the traffic demand. For instance, the system may estimate the future bandwidth needs of each link and reconfigure its data rate to meet those requirements while consuming less power. In one configuration, a mechanism is provided where the switch tracks the utilization of each of its links over an epoch, and then makes an adjustment at the end of the epoch.
摘要翻译：为诸如数据中心的计算机网络提供能量比例解决方案。拥塞感知启发式用于自适应地跨链路路由流量。检测到交通强度，并根据需要动态激活链路。随着提供的负载减小，感测到较低的信道利用率，并且减少链路速度以节省功率。扁平蝶形拓扑可以用于进一步节能方法。交换机制通过重新配置链路速度来快速利用拓扑的功能，以匹配带宽和功率与流量需求。例如，系统可以估计每个链路的未来带宽需求，并重新配置其数据速率以满足这些要求，同时消耗更少的功率。在一种配置中，提供了一种机制，其中开关在历元上跟踪其每个链接的利用率，然后在时代结束时进行调整。

4. 发明申请

US20120170582A1 SYSTEMS AND METHODS FOR DYNAMIC ROUTING IN A MULTIPROCESSOR NETWORK USING LOCAL CONGESTION SENSING 有权
标题翻译：使用本地约束感测的多处理器网络中的动态路由的系统和方法
公开(公告)号：US20120170582A1
公开(公告)日：2012-07-05
申请号：US12985013
申请日：2011-01-05
申请人： Dennis Charles Abts , Peter Michael Klausler , Michael Marty , Philip Wells
发明人： Dennis Charles Abts , Peter Michael Klausler , Michael Marty , Philip Wells
IPC分类号： H04L12/56
CPC分类号： H04L45/06 , H04L45/125 , H04L47/122
摘要： Adaptive packet routing is employed in a multiprocessor network configuration such as an InfiniBand switch architecture. Packets are routed from host to host through one or more switches. Upon receipt of a packet at a switch, the packet header is inspected to determine the destination host. A destination field in the header is used to index into a lookup table or other memory, which produces a route type and an output port grouping. Depending on the route type, one or more primary and secondary output port candidates are identified. An output port arbitration module chooses an output port from which to send a given packet, using congestion sensing inputs for the specified ports. A heuristic may include the congestion information that is provided to the arbitration module. Switching may be performed among minimal or non-minimal routes along each hop in the path, depending upon link and packet injection information.
摘要翻译：在多处理器网络配置（如InfiniBand交换机架构）中采用自适应数据包路由。数据包通过一个或多个交换机从主机路由到主机。在交换机接收到分组时，检查分组报头以确定目的主机。标题中的目的地字段用于索引到查找表或其他内存，这产生路由类型和输出端口分组。根据路由类型，识别一个或多个主输出端口和辅助输出端口候选。输出端口仲裁模块使用用于指定端口的拥塞感知输入来选择从其发送给定分组的输出端口。启发式可以包括提供给仲裁模块的拥塞信息。取决于链路和分组注入信息，可以在路径中的每一跳的最小或非最小路由之间进行切换。

5. 发明授权

US08441933B2 Deadlock prevention in direct networks of arbitrary topology 有权
公开(公告)号：US08441933B2
公开(公告)日：2013-05-14
申请号：US13366722
申请日：2012-02-06
申请人： Peter Michael Klausler
发明人： Peter Michael Klausler
IPC分类号： H04L1/00 , H04L12/26 , H04L12/28 , H04L12/56
CPC分类号： H04L47/12 , G06F15/17312 , G06F15/17381 , H04L45/06 , H04L45/18 , H04L45/60 , H04L49/253
摘要： Aspects of the invention pertain to routing packets in a computer system while avoiding deadlock. A turn rule is set according to unique identifiers associated with switches in the system. Numeric values of switches in possible turns are compared to determine whether a turn is permissible. The rule applies to all nodes in the system. The rule may be violated when using virtual channels. Here, a violation is permissible when using monotonically increasing virtual channel numbers or monotonically decreasing virtual channel numbers. Alternatively, the violations of the turn rule may be allowed if they force a packet to change to a later virtual channel in some fixed ordering of virtual channels. Deadlock can thus be avoided in many different types of architectures, including mesh, torus, butterfly and flattened butterfly configurations.

6. 发明授权

US06308250B1 Method and apparatus for processing a set of data values with plural processing units mask bits generated by other processing units 失效
标题翻译：用于处理具有多个处理单元的一组数据值掩蔽由其他处理单元生成的位的方法和装置
公开(公告)号：US06308250B1
公开(公告)日：2001-10-23
申请号：US09103201
申请日：1998-06-23
申请人： Peter Michael Klausler
发明人： Peter Michael Klausler
IPC分类号： G06F1500
CPC分类号： G06F9/30018 , G06F9/30036 , G06F9/3842 , G06F9/3885
摘要： A method and system for operating a computing system having multiple processing units. According to a new machine instruction, called the iota instruction, the computing system operates on a vector of mask bits to generate an iota vector having a sequence of values. In one form, each value of the iota vector is a sum of a series of the lower order mask bits up to and including the mask bit corresponding to the entry in the iota vector. In another form, each entry in the iota vector is a sum of a series of lower order mask bits but does not include the mask bit corresponding to the particular entry in the iota vector. In order to calculate the iota vector, the multiple processing units of the present invention communicate the mask bits to the other processing units. Advantages of the present invention include the vectorization of software loops having certain data hazards that prevented conventional compilers from vectorizing the software.
摘要翻译：一种用于操作具有多个处理单元的计算系统的方法和系统。根据称为iota指令的新机器指令，计算系统对掩码位的向量进行操作以生成具有值序列的iota向量。在一种形式中，iota向量的每个值是直到并包括对应于iota向量中的条目的掩码位的一系列低阶掩码位的和。在另一种形式中，iota向量中的每个条目是一系列低阶掩码位的和，但不包括对应于iota向量中的特定条目的掩码位。为了计算iota向量，本发明的多个处理单元将掩码比特传送给其他处理单元。本发明的优点包括具有某些数据危害的软件循环的矢量化，防止常规编译器对软件进行向量化。

7. 发明授权

US09450775B1 System and method for bouncing traffic in deadlock safe manner 有权
标题翻译：以僵死的方式弹起交通的系统和方法
公开(公告)号：US09450775B1
公开(公告)日：2016-09-20
申请号：US13552914
申请日：2012-07-19
申请人： Peter Michael Klausler , Philip Michael Wells
发明人： Peter Michael Klausler , Philip Michael Wells
IPC分类号： H04L12/28 , H04L12/26
CPC分类号： H04L12/26 , H04L45/04 , H04L45/22 , H04L45/58
摘要： A network may be configured to route traffic in such a way as to avoid packet loss in an event of link failure. The network may include a plurality of inner switches and a plurality of outer switches coupled to the plurality of inner switches. Each inner switch may be configured to receive traffic, determine whether a link to a next hop for the traffic is down, and forward the traffic to another outer switch if the link to the next hop is down. Each outer switch may be configured to bounce traffic received from the first inner switch to a second inner switch if the traffic is received as a result of determining that the link from the inner switch to the next hop is down. The second inner switch may then deliver the traffic, or further bounce the traffic off another outer switch.
摘要翻译：网络可以被配置为以在链路故障的情况下避免分组丢失的方式来路由业务。网络可以包括多个内部开关和耦合到多个内部开关的多个外部开关。每个内部交换机可以被配置为接收流量，确定到流量的下一跳的链路是否关闭，并且如果到下一跳的链路断开，则将流量转发到另一个外部交换机。每个外部交换机可以被配置为如果通过确定从内部交换机到下一跳的链路关闭而接收到业务，则将从第一内部交换机接收的业务反弹到第二内部交换机。然后，第二内部交换机可以传送业务，或进一步使业务从另一外部交换机反弹。

8. 发明授权

US08730965B2 Systems and methods for dynamic routing in a multiprocessor network using local congestion sensing 有权
标题翻译：使用局部拥塞感知在多处理器网络中进行动态路由的系统和方法
公开(公告)号：US08730965B2
公开(公告)日：2014-05-20
申请号：US12985013
申请日：2011-01-05
申请人： Dennis Charles Abts , Peter Michael Klausler , Michael Marty , Philip Wells
发明人： Dennis Charles Abts , Peter Michael Klausler , Michael Marty , Philip Wells
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/06 , H04L45/125 , H04L47/122
摘要： Adaptive packet routing is employed in a multiprocessor network configuration such as an InfiniBand switch architecture. Packets are routed from host to host through one or more switches. Upon receipt of a packet at a switch, the packet header is inspected to determine the destination host. A destination field in the header is used to index into a lookup table or other memory, which produces a route type and an output port grouping. Depending on the route type, one or more primary and secondary output port candidates are identified. An output port arbitration module chooses an output port from which to send a given packet, using congestion sensing inputs for the specified ports. A heuristic may include the congestion information that is provided to the arbitration module. Switching may be performed among minimal or non-minimal routes along each hop in the path, depending upon link and packet injection information.
摘要翻译：在多处理器网络配置（如InfiniBand交换机架构）中采用自适应数据包路由。数据包通过一个或多个交换机从主机路由到主机。在交换机接收到分组时，检查分组报头以确定目的主机。标题中的目的地字段用于索引到查找表或其他内存，这产生路由类型和输出端口分组。根据路由类型，识别一个或多个主输出端口和辅助输出端口候选。输出端口仲裁模块使用用于指定端口的拥塞感知输入来选择从其发送给定分组的输出端口。启发式可以包括提供给仲裁模块的拥塞信息。取决于链路和分组注入信息，可以在路径中的每一跳的最小或非最小路由之间进行切换。

9. 发明申请

US20120140631A1 DEADLOCK PREVENTION IN DIRECT NETWORKS OF ARBITRARY TOPOLOGY 有权
标题翻译：直接网络中的死亡预防措施
公开(公告)号：US20120140631A1
公开(公告)日：2012-06-07
申请号：US13366722
申请日：2012-02-06
申请人： Peter Michael Klausler
发明人： Peter Michael Klausler
IPC分类号： H04L12/22
CPC分类号： H04L47/12 , G06F15/17312 , G06F15/17381 , H04L45/06 , H04L45/18 , H04L45/60 , H04L49/253
摘要： Aspects of the invention pertain to routing packets in a computer system while avoiding deadlock. A turn rule is set according to unique identifiers associated with switches in the system. Numeric values of switches in possible turns are compared to determine whether a turn is permissible. The rule applies to all nodes in the system. The rule may be violated when using virtual channels. Here, a violation is permissible when using monotonically increasing virtual channel numbers or monotonically decreasing virtual channel numbers. Alternatively, the violations of the turn rule may be allowed if they force a packet to change to a later virtual channel in some fixed ordering of virtual channels. Deadlock can thus be avoided in many different types of architectures, including mesh, torus, butterfly and flattened butterfly configurations.
摘要翻译：本发明的方面涉及在计算机系统中路由分组，同时避免死锁。根据与系统中的开关相关联的唯一标识符设置转弯规则。比较可能转弯中开关的数值，以确定转弯是否允许。该规则适用于系统中的所有节点。使用虚拟通道时可能会违反规则。这里，当使用单调递增的虚拟通道号或单调递减虚拟通道号时，允许违规。或者，如果在某些固定的虚拟通道排序中强制分组改变为稍后的虚拟通道，则可能允许违反转弯规则。因此，可以在许多不同类型的架构中避免死锁，包括网格，环面，蝴蝶和扁平蝶形配置。

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