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1. 发明申请

US20070132062A1 Electronic apparatus interconnect routing and interconnect routing method for minimizing parasitic resistance 有权
标题翻译：用于最小化寄生电阻的电子设备互连路由和互连路由方法
公开(公告)号：US20070132062A1
公开(公告)日：2007-06-14
申请号：US11302007
申请日：2005-12-09
申请人： Suman Banerjee , Alain Duvallet , Olin Hartin , Craig Jasper , Walter Parmon
发明人： Suman Banerjee , Alain Duvallet , Olin Hartin , Craig Jasper , Walter Parmon
IPC分类号： H01L29/00
CPC分类号： H01L23/528 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Method and apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.
摘要翻译：提供了用于路由以差分配置工作的双门电子设备的互连的方法和装置。提供了一种形成在基板上的电子设备，包括被配置为耦合到所述基板的第一区域的第一互连（40,42,44），耦合到所述第一互连并配置的第一栅极（22,24,26,28）接收第一差分输入，平行于第一互连并被配置为耦合到衬底的第二区域的第二互连（30,32,34,36,38）以及耦合到第二互连的第二栅极（20）并且被配置为接收第二差分输入。第一栅极平行于第一互连，第二栅极平行于第二互连。

2. 发明申请

US20060214238A1 Multi-gate enhancement mode RF switch and bias arrangement 有权
标题翻译：多栅极增强模式RF开关和偏置布置
公开(公告)号：US20060214238A1
公开(公告)日：2006-09-28
申请号：US11092264
申请日：2005-03-28
申请人： Elizabeth Glass , Olin Hartin , Neil Tracht
发明人： Elizabeth Glass , Olin Hartin , Neil Tracht
IPC分类号： H01L29/76
CPC分类号： H01L27/0605 , H01L23/4824 , H01L29/42316 , H01L29/7786 , H01L2924/0002 , H01L2924/3011 , H04B1/48 , H01L2924/00
摘要： Methods and apparatus are provided for RF switches (100, 200). In a preferred embodiment, the apparatus comprises one or more multi-gate n-channel enhancement mode FET transistors (50, 112, 114). When used in pairs (112, 114) each has its source (74, 133) coupled to a first common RF I/O port (116) and drains coupled respectively to second and third RF I/O ports (118, 120), and gates (136, 138), coupled respectively to first and second control terminals (122, 124). The multi-gate regions (66, 68) of the FETs (50) are parallel coupled, spaced-apart and serially arranged between source (72) and drain (76). Lightly doped n-regions (Ldd, Lds) are provided serially arranged between the spaced-apart multi-gate regions (66, 68), the lightly doped n-regions (Ldd, Lds) being separated by more heavily doped n-regions (84). Bias resistances (132, 134) are provided between the sources (72, 133) and control terminals (122, 124) so as to provide a DC path between the control terminals (122, 124) that maintains the source (72, 133) voltage at the proper bias potential for enhancement mode operation.
摘要翻译：提供了用于RF开关（100,200）的方法和装置。在优选实施例中，该装置包括一个或多个多栅极n沟道增强型FET晶体管（50,112,114）。当成对使用时，每个都具有耦合到第一公共RF I / O端口（116）的源极（74,133）和分别耦合到第二和第三RF I / O端口（118,120）的漏极，和分别耦合到第一和第二控制端（122,124）的门（136,138）。 FET（50）的多栅极区域（66,68）平行耦合，间隔开并且串联地布置在源极（72）和漏极（76）之间。轻度掺杂的n区（Ldd，Lds）被串行地布置在间隔开的多栅极区（66,68）之间，轻掺杂的n-区（Ldd，Lds）被更重掺杂的n区分离（ 84）。偏置电阻（132,134）设置在源极（72,133）和控制端子（122,124）之间，以便在维持源极（72,133）和控制端子（122,124）之间提供DC路径，电压处于适当的偏置电位，用于增强模式操作。

3. 发明申请

US20060043416A1 Recessed semiconductor device 有权
标题翻译：嵌入式半导体器件
公开(公告)号：US20060043416A1
公开(公告)日：2006-03-02
申请号：US10925855
申请日：2004-08-25
申请人： Hsin-Hua P. Li , Bruce Green , Olin Hartin , Ellen Lan , Charles Weitzel
发明人： Hsin-Hua P. Li , Bruce Green , Olin Hartin , Ellen Lan , Charles Weitzel
IPC分类号： H01L31/0328
CPC分类号： H01L29/7785 , H01L21/28593 , H01L29/2003 , H01L29/66462
摘要： A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.
摘要翻译：半导体结构包括第一半导体层，第一半导体层上的第二半导体层，第二半导体层上的第三半导体层以及第三半导体层上的第四半导体层。第一导电部分耦合到第一半导体层，并且在第一半导体层上形成第二导电部分。

4. 发明授权

US06479843B2 Single supply HFET with temperature compensation 有权
标题翻译：单电源HFET具有温度补偿功能
公开(公告)号：US06479843B2
公开(公告)日：2002-11-12
申请号：US09559791
申请日：2000-04-27
申请人： Jenn-Hwa Huang , Elizabeth C. Glass , Olin Hartin , Wendy L. Valentine , Julio Costa
发明人： Jenn-Hwa Huang , Elizabeth C. Glass , Olin Hartin , Wendy L. Valentine , Julio Costa
IPC分类号： H01L21338
CPC分类号： H01L21/8252 , H01L27/0248 , H01L27/0605 , H03F1/301 , H03K17/145
摘要： A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.
摘要翻译：一种制造装置的方法和装置，用于在单个电源HFET中提供低电压温度补偿，所述单电源HFET包括在叠层中形成的具有HFET的外延生长的化合物半导体层的堆叠。在形成HFET期间，在与HFET相邻的堆叠中形成肖特基二极管。 HFET和肖特基二极管同时形成，形成HFET的栅极的一层金属的一部分定位成与具有低带隙（例如小于0.8eV）的堆叠层接触，以提供肖特基二极管的导通电压小于1.8伏。肖特基二极管通过栅极电路连接到HFET的栅极接触，以补偿栅极电路中随着温度变化的电流负载的变化。

5. 发明申请

US20130277680A1 High Speed Gallium Nitride Transistor Devices 有权
标题翻译：高速氮化镓晶体管器件
公开(公告)号：US20130277680A1
公开(公告)日：2013-10-24
申请号：US13453127
申请日：2012-04-23
申请人： Bruce M. Green , Karen E. Moore , Olin Hartin
发明人： Bruce M. Green , Karen E. Moore , Olin Hartin
IPC分类号： H01L29/20 , H01L21/336
CPC分类号： H01L29/7787 , H01L27/0629 , H01L28/60 , H01L29/2003 , H01L29/402 , H01L29/404 , H01L29/42316 , H01L29/42376 , H01L29/475 , H01L29/66462
摘要： A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-13) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).
摘要翻译：提供了一种低泄漏电流开关装置（110），其包括由钝化表面层（43）覆盖的GaN-Si衬底（11-13），其中形成具有侧壁延伸部（48）的T形栅电极，涂覆有共形钝化层（49），使得T栅极电极侧壁延伸部通过共形钝化层（49）与下面的钝化表面层（43）间隔开。

6. 发明申请

US20060267133A1 INTEGRATED CIRCUIT WITH IMPROVED SIGNAL NOISE ISOLATION AND METHOD FOR IMPROVING SIGNAL NOISE ISOLATION 有权
标题翻译：具有改进的信号噪声隔离的集成电路和用于改善信号噪声隔离的方法
公开(公告)号：US20060267133A1
公开(公告)日：2006-11-30
申请号：US11142433
申请日：2005-05-31
申请人： Suman Banerjee , Enrique Ferrer , Olin Hartin , Radu Secareanu
发明人： Suman Banerjee , Enrique Ferrer , Olin Hartin , Radu Secareanu
IPC分类号： H01L29/00
CPC分类号： H01L27/0248 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A system-on chip (SOC) (100) and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks (120, 220) and ESD protected pads (302, 304, 306, 308, 310, 312, and 314). A VDD isolation pad (302) is connected to an N well ring (124) of the first noise sensitive circuit (120) to collect noise from the substrate (110) and isolate the circuit from the P well region (112). A ground protected pad (304) is connected to an isolated P well (126) of a first noise sensitive circuit (120). The ground pad (304) collects noise from the isolated P well (126) and sends it to ground. A dedicated ground isolation pad (306) is connected to a P well ring (224) of a second noise sensitive circuit (220). The dedicated ground isolation pad (306) collects noise from the P well ring (224) and sends it to ground. The dedicated ground isolation pad (306) and the ground pad (304) collect noise that would normally propagate between the first and second noise sensitive circuits (120, 220) and additional circuits that share the same substrate (110).
摘要翻译：一种片上系统（SOC）（100）以及分离SOC中的噪声的方法，包括多个噪声敏感电路块（120,220）和ESD保护焊盘（302,304,306,308,310,312,312）和314）。 VDD隔离焊盘（302）连接到第一噪声敏感电路（120）的N阱环（124），以从基板（110）收集噪声，并将电路与P阱区域（112）隔离。接地保护焊盘（304）连接到第一噪声敏感电路（120）的隔离P阱（126）。接地焊盘（304）从隔离的P阱（126）收集噪声并将其发送到地面。专用接地隔离垫（306）连接到第二噪声敏感电路（220）的P阱环（224）。专用接地隔离垫（306）从P阱环（224）收集噪声并将其发送到地面。专用接地隔离焊盘（306）和接地焊盘（304）收集正常地在第一和第二噪声敏感电路（120,220）之间传播的噪声以及共享相同衬底（110）的附加电路。

7. 发明申请

US20060270164A1 Method of making planar double gate silicon-on-insulator structures 有权
标题翻译：制造平面双栅硅绝缘体上结构的方法
公开(公告)号：US20060270164A1
公开(公告)日：2006-11-30
申请号：US11142057
申请日：2005-05-31
申请人： Philip Li , Suman Banerjee , Thuy Dao , Olin Hartin , Jay John
发明人： Philip Li , Suman Banerjee , Thuy Dao , Olin Hartin , Jay John
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/66628 , H01L29/66772 , H01L29/78648
摘要： Methods are provided for forming a semiconductor device from a substrate comprising a bottom gate layer, a channel layer overlying the bottom gate layer, and a top gate structure formed over the channel layer. First, a hardmask comprising a first material interposed between a second material and a third material is deposited over a portion of the top gate structure. Then, the hardmask and top gate structure are encapsulated with an insulating material to form a spacer. A channel structure is formed from the channel layer, and the channel structure is disposed under the spacer. A bottom gate structure is formed from the bottom gate layer, and the bottom gate structure is disposed under the channel structure. Then, a source/drain contact is formed around the bottom gate structure.
摘要翻译：提供了用于从包括底栅层，覆盖底栅层的沟道层和形成在沟道层上的顶栅结构的衬底形成半导体器件的方法。首先，在顶部栅极结构的一部分上沉积包括介于第二材料和第三材料之间的第一材料的硬掩模。然后，硬掩模和顶栅结构用绝缘材料封装以形成间隔物。沟道结构由沟道层形成，并且沟道结构设置在间隔物的下方。底栅结构由底栅层形成，底栅结构设置在沟道结构下。然后，在底栅结构周围形成源极/漏极接触。

8. 发明申请

US20060217078A1 Enhancement mode transceiver and switched gain amplifier integrated circuit 有权
标题翻译：增强型收发器和开关增益放大器集成电路
公开(公告)号：US20060217078A1
公开(公告)日：2006-09-28
申请号：US11092070
申请日：2005-03-28
申请人： Elizabeth Glass , Olin Hartin , Ngai Lau , Neil Tracht
发明人： Elizabeth Glass , Olin Hartin , Ngai Lau , Neil Tracht
IPC分类号： H04B1/44 , H04B1/28
CPC分类号： H03G1/0088
摘要： Methods and apparatus are provided for RF switches (504, 612) integrated in a monolithic RF transceiver IC (500) and switched gain amplifier (600). Multi-gate n-channel enhancement mode FETs (50, 112, 114, Q1-3, Q4-6) are used with single gate FETs (150), resistors (Rb, Rg, Re, R1-R17) and capacitors (C1-C3) formed by the same manufacturing process. The multiple gates (68) of the FETs (50, 112, 114, Q1-3, Q4-6) are parallel coupled, spaced-apart and serially arranged between source (72) and drain (76). When used in pairs (112, 114) to form a switch (504) for a transceiver (500) each FET has its source (74) coupled to an antenna RF I/O port (116, 501) and drains coupled respectively to second and third RF I/O ports (118, 120; 507, 521) leading to the receiver side (530) or transmitter side (532) of the transceiver (500). The gates (136, 138) are coupled to control ports (122, 124; 503, 505; 606, 608). When used in pairs (Q1-3, Q4-6) to form a variable switched attenuator, the first FET (Q1-3) is a pass device and the second FET (Q4-6) is a shunt device that respectively bridge two series resistors (R1, R2) and block a shunt resistor (R3) of a T-type attenuator.
摘要翻译：为集成在单片RF收发器IC（500）和开关增益放大器（600）中的RF开关（504,612）提供了方法和装置。多栅极n沟道增强型FET（50,112,114，Q 1-3，Q 4-6）与单栅极FET（150），电阻器（Rb，Rg，Re，R 1 -R 17）和通过相同制造工艺形成的电容器（C 1 -C 3）。 FET（50,112,114，Q1-3，Q4-6）的多个栅极（68）被平行耦合，间隔开并且串联地布置在源极（72）和漏极（76）之间。当成对使用（112,114）形成用于收发器（500）的开关（504）时，每个FET的源极（74）耦合到天线RF I / O端口（116,501），并且分别耦合到第二以及通向收发器（500）的接收机侧（530）或发射机侧（532）的第三RF I / O端口（118,120; 507,521）。门（136,138）被耦合到控制端口（122,124; 503,505; 606,608）。当成对使用（Q 1 - 3，Q 4 - 6）以形成可变开关衰减器时，第一FET（Q1-3）是通过器件，第二FET（Q 4 - 6）是分流器件，分别桥接两个串联电阻（R 1，R 2）并阻塞T型衰减器的分流电阻（R 3）。

9. 发明授权

US09099433B2 High speed gallium nitride transistor devices 有权
标题翻译：高速氮化镓晶体管器件
公开(公告)号：US09099433B2
公开(公告)日：2015-08-04
申请号：US13453127
申请日：2012-04-23
申请人： Bruce M. Green , Karen E. Moore , Olin Hartin
发明人： Bruce M. Green , Karen E. Moore , Olin Hartin
IPC分类号： H01L21/336 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/778 , H01L29/20
CPC分类号： H01L29/7787 , H01L27/0629 , H01L28/60 , H01L29/2003 , H01L29/402 , H01L29/404 , H01L29/42316 , H01L29/42376 , H01L29/475 , H01L29/66462
摘要： A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-13) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).
摘要翻译：提供了一种低泄漏电流开关装置（110），其包括由钝化表面层（43）覆盖的GaN-Si衬底（11-13），其中形成具有侧壁延伸部（48）的T形栅电极，涂覆有共形钝化层（49），使得T栅极电极侧壁延伸部通过共形钝化层（49）与下面的钝化表面层（43）间隔开。

10. 发明申请

US20070194394A1 Noise isolation between circuit blocks in an integrated circuit chip 有权
标题翻译：集成电路芯片中电路块之间的噪声隔离
公开(公告)号：US20070194394A1
公开(公告)日：2007-08-23
申请号：US11360285
申请日：2006-02-23
申请人： Radu Secareanu , Suman Banejee , Olin Hartin
发明人： Radu Secareanu , Suman Banejee , Olin Hartin
IPC分类号： H01L29/76
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/762 , H01L21/765 , H01L21/823481 , H01L29/0619
摘要： An integrated circuit includes a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.
摘要翻译：集成电路包括由于在衬底的区域中形成的低掺杂浓度而具有高电阻率的p阱块区域，用于在第一电路块和第二电路块之间提供噪声隔离。集成电路还包括围绕p阱块区域形成的保护区域，用于在第一电路块和第二电路块之间提供噪声隔离。

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