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    • 1. 发明授权
    • Image forming apparatus
    • 图像形成装置
    • US09244401B2
    • 2016-01-26
    • US12607007
    • 2009-10-27
    • Goichi KitadaiDaisuke MiyagawaNoriyuki ItoTakahiro Uchiyama
    • Goichi KitadaiDaisuke MiyagawaNoriyuki ItoTakahiro Uchiyama
    • G03G15/00G03G15/20
    • G03G15/2042
    • In an image forming apparatus, the overall length of a heat generating resistor is set longer than the width of a recording paper, which is the greatest of widths of standard size recording papers that can be used on the image forming apparatus. An electrical resistance of an edge area of the heat generating resistor per unit length is set smaller than that of a center area of the heat generating resistor. The position of a boundary between the center area and the edge area is set so that the position of the side edge of the recording paper whose width is the greatest exists within the edge area and so that if the recording paper having the second greatest width is fed by a one edge-aligned paper feeding method, the position of the side edge of a recording paper whose width is the greatest of the widths of the standard size recording papers that can be used on the image forming apparatus except the width of the recording paper that is the greatest thereof is set at a position within the center area.
    • 在图像形成装置中,发热电阻器的总长度被设定为比可以用于图像形成装置的标准尺寸的记录纸的宽度最大的记录纸的宽度长。 每单位长度的发热电阻器的边缘区域的电阻被设定为小于发热电阻器的中心区域的电阻。 中心区域和边缘区域之间的边界的位置被设置为使得宽度最大的记录纸的侧边缘的位置存在于边缘区域内,并且如果具有第二大宽度的记录纸是 通过一个边缘对齐的送纸方式进给,其宽度是除了记录宽度之外可以用于图像形成装置的标准尺寸记录纸的宽度的最大的记录纸的侧边缘的位置 其最大的纸被设置在中心区域内的位置。
    • 3. 发明授权
    • Delay analysis device, delay analysis method, and delay analysis program
    • 延迟分析装置,延迟分析方法和延迟分析程序
    • US08407021B2
    • 2013-03-26
    • US12893362
    • 2010-09-29
    • Noriyuki Ito
    • Noriyuki Ito
    • G06F19/00
    • G06F17/5031
    • A delay analysis device includes an acquisition section that acquires circuit information relating to a path through which signal propagation can be delayed, a determination section that sets up an assumed fault for each of pins disposed in the path, and determines whether a signal change output from a beginning latch can be propagated to an ending latch for each of pins for which the assumed faults are set up, and an analysis section that calculates a delay distribution by accumulating delay distributions expressed by probability density functions of delays that occur in individual delay elements included in the path determined that a signal change output from the beginning latch can be propagated to the ending latch, and by not accumulating the delay distributions at a pin through which it has been determined that the signal change cannot be propagated to the ending latch based on the acquired circuit information.
    • 延迟分析装置包括:获取部,其获取与可以延迟信号传播的路径有关的电路信息;确定部,其针对设置在路径中的每个引脚设置假设故障,并且确定是否从 可以将开始锁存器传播到针对假设故障建立的每个引脚的结束锁存器,以及分析部件,其通过累积由包括在各个延迟元件中出现的延迟的概率密度函数所表示的延迟分布来计算延迟分布 在该路径中,确定从开始锁存器输出的信号变化可以传播到结束锁存器,并且通过不在其引脚上累积延迟分布,通过该引脚已经确定信号改变不能传播到结束锁存器,基于 获取的电路信息。
    • 6. 发明授权
    • Method and apparatus for designing integrated circuit
    • 集成电路设计方法和装置
    • US07757188B2
    • 2010-07-13
    • US11785430
    • 2007-04-17
    • Noriyuki Ito
    • Noriyuki Ito
    • G06F17/50
    • G06F17/5045
    • In the present invention, a block level net list is separated from a chip level net list so that the chip level net list can be created in a form in which a block is transparent to a designer. The present invention determines a destination block for circuit elements that are described in a chip level net list and for which the destination block is not determined, and creates a final net list by reflecting the chip level net list to the block level net list based on the information on the destination block. As a net list can be created in a form in which a block is transparent to a designer for a circuit system that is required to be optimized for the entire chip, the circuit system can be efficiently optimized.
    • 在本发明中,将块级网表从芯片级网表中分离出来,使得可以以块对设计者透明的形式来创建芯片级网表。 本发明确定在芯片级网表中描述的电路元件的目的地块,并且未确定目的地块,并且通过基于块级网络列表反映芯片级网络列表来创建最终网列表 目的地块上的信息。 由于网络列表可以以对于需要针对整个芯片进行优化的电路系统的设计者是透明的形式来创建,所以可以有效地优化电路系统。
    • 7. 发明授权
    • Image forming apparatus
    • 图像形成装置
    • US07650091B2
    • 2010-01-19
    • US12133670
    • 2008-06-05
    • Noriyuki ItoKenichi OgawaRikuo Kawakami
    • Noriyuki ItoKenichi OgawaRikuo Kawakami
    • G03G15/20
    • G03G15/2042G03G2215/00721G03G2215/00734
    • An image forming apparatus has a heat member configured so that a longitudinal center becomes a conveyance center of the recording material, the apparatus also having a central portion temperature detection part for detecting a temperature of the heat member corresponding to the conveyance center or adjacent thereto, a one side end portion temperature detection part for detecting one end portion temperature at one side in a longitudinal direction of the heat member, and an other side end portion temperature detection part for detecting an other end portion temperature on the other side in the longitudinal direction of the heat member, and a control part for controlling the image forming apparatus based on heat member temperature information detected by the central portion temperature detection part, the one side end portion temperature detection part, and the other side end portion temperature detection part.
    • 图像形成装置具有加热构件,其构造成纵向中心成为记录材料的输送中心,该装置还具有用于检测对应于输送中心或与其相邻的加热构件的温度的中心部分温度检测部, 一个侧端部温度检测部,用于检测加热部件的长度方向的一端的一端部温度,另一个侧端部温度检测部,用于检测长度方向另一侧的另一端部温度 以及控制部,其基于由中央部温度检测部,一侧端部温度检测部和另一侧端部温度检测部检测出的加热部件温度信息来控制图像形成装置。
    • 9. 发明申请
    • IMAGE FORMING APPARATUS
    • 图像形成装置
    • US20080240803A1
    • 2008-10-02
    • US12133670
    • 2008-06-05
    • NORIYUKI ITOKENICHI OGAWARIKUO KAWAKAMI
    • NORIYUKI ITOKENICHI OGAWARIKUO KAWAKAMI
    • G03G15/20
    • G03G15/2042G03G2215/00721G03G2215/00734
    • The image forming apparatus has a heat member for heating an unfixed image and is configured so that a longitudinal center of the heat member becomes a conveyance center of the recording material, the image forming apparatus including a central portion temperature detection part adjacent to the conveyance center, an end portion temperature detection part for detecting an end portion temperature of the heat member, and a width detection part for detecting a lateral width of the recording material, wherein the width detection part is disposed at a side opposite to a side at which the end portion temperature detection part is disposed with respect to the conveyance center position of the recording material. The image forming apparatus achieves the control for error setting of the recording material based on the width detection part and the end portion temperature detection part.
    • 图像形成装置具有用于加热未定影图像的加热构件,并且构造成使得加热构件的纵向中心成为记录材料的输送中心,图像形成装置包括邻近输送中心的中心部分温度检测部 ,用于检测加热部件的端部温度的端部温度检测部分和用于检测记录材料的横向宽度的宽度检测部分,其中宽度检测部分设置在与该部件的一侧相反的一侧, 端部温度检测部相对于记录材料的输送中心位置配置。 图像形成装置基于宽度检测部和端部温度检测部实现记录材料的误差设定的控制。
    • 10. 发明申请
    • Method and apparatus for analyzing delay defect
    • 分析延迟缺陷的方法和装置
    • US20080072108A1
    • 2008-03-20
    • US11709256
    • 2007-02-22
    • Noriyuki Ito
    • Noriyuki Ito
    • G11B20/20
    • G01R31/3016
    • The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual increase in the frequency of an operational clock pulse fed to an integrated circuit belongs. The apparatus obtains information on latch in which an error is caused with the RC of the maximal incidence, with reference to a mapping table that describes the mapping relationship between an RC and a latch. The apparatus extracts a circuit portion in which an error can be captured with the region code of the maximal incidence by exhaustively tracing back circuit portions connected with each obtained latch, from the latch to the latch described in the mapping table. The apparatus gives delay defects to the input and the output pin of each of logic elements included in the extracted circuit portion, generates test patterns for detecting the given delay defects, and performs delay tests.
    • 用于分析本发明的延迟缺陷的装置获得区域码(RC)中的最大入射的RC,其中检测电路检测由馈送到集成电路的工作时钟脉冲的频率逐渐增加所引起的错误。 参考描述RC和锁存器之间映射关系的映射表,该装置获得关于最大入射的RC导致错误的锁存信息。 该装置从映射表中描述的锁存器到锁存器,通过穷举地跟踪与每个获得的锁存器连接的回路部分,以最大入射的区域码来捕获误差的电路部分。 该装置给包括在提取的电路部分中的每个逻辑元件的输入和输出引脚提供延迟缺陷,产生用于检测给定延迟缺陷的测试图案,并进行延迟测试。