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1. 发明授权

US07480416B2 Implementation of discrete wavelet transform using lifting steps 失效
标题翻译：使用提升步骤实现离散小波变换
公开(公告)号：US07480416B2
公开(公告)日：2009-01-20
申请号：US10435499
申请日：2003-05-09
申请人： Hongyu Liao , Mrinal K. Mandal , Bruce F. Cockburn
发明人： Hongyu Liao , Mrinal K. Mandal , Bruce F. Cockburn
IPC分类号： G06K9/36 , G06K9/46 , G06K9/40 , H04B1/66 , H04N11/02 , H04N11/04 , H04N7/12
CPC分类号： G06F17/148
摘要： Compact and efficient hardware architectures for implementing lifting-based DWTs, including 1-D and 2-D versions of recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a 5-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array. The 2-D dual scan architecture processes the column and row transforms simultaneously, and the memory buffer size is comparable to existing architectures. The recursive and dual scan architectures can be readily extended to the N-D case.
摘要翻译：紧凑且高效的硬件架构，用于实现基于升级的DWT，包括递归和双扫描架构的1-D和2-D版本。 1-D递归架构通过交织利用相互依赖关系，在使用相同数据路径硬件的交替时钟周期上，计算较高阶系数以及第一阶段系数。在典型情况下，在1024个样本上运行的5级1-DWT DWT，所得到的硬件利用率将超过90％。 1-D双扫描架构通过使用共享功能块处理两个独立数据流来实现100％的数据路径硬件利用率。 2-D递归架构比传统实现快25％，它需要一个只存储几行数据的缓冲区，而不是整个阵列的固定分数（通常为25％或更多）。 2-D双扫描架构同时处理列和行变换，并且内存缓冲区大小与现有架构相当。递归和双重扫描架构可以容易地扩展到N-D情况。

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