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1. 发明授权

US08514873B2 Advanced telecommunications router and crossbar switch controller 有权
标题翻译：先进的电信路由器和交叉开关控制器
公开(公告)号：US08514873B2
公开(公告)日：2013-08-20
申请号：US12890551
申请日：2010-09-24
申请人： Brian Hang Wai Yang , Kai-Yeung (Sunny) Siu , Mizanur M. Rahman , Wei-Han Lien , Gaurav Singh
发明人： Brian Hang Wai Yang , Kai-Yeung (Sunny) Siu , Mizanur M. Rahman , Wei-Han Lien , Gaurav Singh
IPC分类号： H04L12/54
CPC分类号： H04L49/25 , H04L49/101 , H04L49/3027 , H04L49/3045
摘要： An apparatus and method to receive first service request signals and second service request signals from virtual signal queues, to map the virtual signal queues according to a first mapping, to arbitrate the first service request signals in accordance with the first mapping of the virtual signal queues, and to re-map the virtual signal queues according to a second mapping, different from the first mapping, to allow arbitrating of the second service request signals in accordance with the second mapping of the virtual signal queues.
摘要翻译：一种从虚拟信号队列接收第一服务请求信号和第二服务请求信号的装置和方法，以根据第一映射映射虚拟信号队列，以根据虚拟信号队列的第一映射来仲裁第一服务请求信号并且根据与第一映射不同的第二映射来重新映射虚拟信号队列，以允许根据虚拟信号队列的第二映射来仲裁第二服务请求信号。

2. 发明申请

US20090034517A1 ADVANCED TELECOMMUNICATIONS ROUTER AND CROSSBAR SWITCH CONTROLLER 失效
标题翻译：高级电信路由器和交叉开关控制器
公开(公告)号：US20090034517A1
公开(公告)日：2009-02-05
申请号：US12170269
申请日：2008-07-09
申请人： Brian Hang Wai Yang , Kai-Yeung (Sunny) Siu , Mizanur M. Rahman , Wei-Han Lien , Gaurav Singh
发明人： Brian Hang Wai Yang , Kai-Yeung (Sunny) Siu , Mizanur M. Rahman , Wei-Han Lien , Gaurav Singh
IPC分类号： H04L12/50
CPC分类号： H04L49/25 , H04L49/101 , H04L49/3027 , H04L49/3045
摘要： The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements. Whereby, the arbiter circuit scans the matrix during a first epoch, issues the set of grant signals, allows the set of granted service requests to substantially complete, and if necessary, scans the matrix during subsequent epochs. The invention also relates to a crossbar switch controller including an arbitration pre-processor coupled to the input terminal and the matrix circuit, and configured to represent the set of service request signals in the form of a mapping matrix, and further configured to transform a first mapping position of the service request signal to a second mapping position based, in part, on a mapping algorithm. The invention also includes an arbitration post-processor coupled to the output terminal and the matrix circuit, and further configured to transform the second mapping position of the service request signal back to the first mapping position.
摘要翻译：本发明涉及一种交叉开关控制器，其包括输入端子，该输入端子被配置为从包括一组分组的一组虚拟输出队列接收一组服务请求信号。本发明还包括耦合到输入端并被配置为以矩阵的形式表示服务请求信号集合的矩阵电路，其中每个服务请求信号由行位置M和列位置N描述。本发明进一步包括被配置为在历元期间接收所述一组分组的一部分的输出终端，所述仲裁器电路被配置为在所述时期期间迭代地扫描所述矩阵，并向所述虚拟输出队列发出所述一组授权信号以确定哪些服务请求被授权，以及仲裁器控制器，被配置为使用非冲突矩阵元素的阵列启动仲裁器电路。由此，仲裁器电路在第一纪元期间扫描矩阵，发出授权信号集合，允许一组授权的服务请求基本上完成，并且如果需要，在随后的时期期间扫描矩阵。本发明还涉及一种交叉开关控制器，其包括耦合到输入端和矩阵电路的仲裁预处理器，并且被配置为以映射矩阵的形式表示该组服务请求信号，并且还被配置为将第一部分地基于映射算法将服务请求信号的映射位置映射到第二映射位置。本发明还包括耦合到输出端和矩阵电路的仲裁后处理器，还被配置为将服务请求信号的第二映射位置转换回第一映射位置。

3. 发明授权

US5765007A Microinstruction sequencer having multiple control stores for loading different rank registers in parallel 失效
标题翻译：微指令定序器具有多个用于并行加载不同等级寄存器的控制存储器
公开(公告)号：US5765007A
公开(公告)日：1998-06-09
申请号：US976304
申请日：1992-11-13
申请人： Mizanur M. Rahman , Robert W. Horst , Richard Harris
发明人： Mizanur M. Rahman , Robert W. Horst , Richard Harris
IPC分类号： G06F9/22 , G06F9/26 , G06F9/28
CPC分类号： G06F9/26 , G06F9/28
摘要： First and second banks of control stores are used to store microinstructions. Each bank contains three control stores: A horizontal control store, a vertical control store, and a jump control store. The horizontal control store contains the rank four microcode; the vertical control store contains the rank three microcode; and the jump control store contains the same microcode as the vertical control store but is used on conditional jump microoperations. This allows simultaneous accessing of different microinstructions using a single address incrementer. The control store banks are accessed in an overlapping manner so that upon each clock cycle one bank is loading the rank 3 and rank 4 registers. The sequencer according to the present invention includes a return address stack for returning from subroutine calls and trap routines. When processing trap routines, the return address stack stores two microinstruction addresses to allow processing of a previously encountered jump or call operation that may have been aborted when the trap routine was entered.
摘要翻译：第一和第二控制柜门用于存储微指令。每个银行包含三个控制存储：水平控制存储，垂直控制存储和跳转控制存储。水平控制存储包含四级微码; 垂直控制商店包含三级微码; 并且跳转控制存储器包含与垂直控制存储器相同的微代码，但是用于条件跳转微操作。这允许使用单个地址增量器同时访问不同的微指令。以重叠的方式访问控制存储体，使得在每个时钟周期中，一个存储体正在加载等级3和等级4寄存器。根据本发明的定序器包括用于从子程序调用和陷阱例程返回的返回地址堆栈。当处理陷阱例程时，返回地址堆栈存储两个微指令地址，以允许处理先前遇到的跳转或调用操作，当进入陷阱程序时可能已经中止了跳转或调用操作。

4. 发明授权

US5590337A Processor interface chip for dual-microprocessor processor system 失效
公开(公告)号：US5590337A
公开(公告)日：1996-12-31
申请号：US426365
申请日：1995-04-21
申请人： Mizanur M. Rahman , Fred C. Sabernick , Jeff A. Sprouse , Martin J. Grosz , Peter Fu , Russell M. Rector
发明人： Mizanur M. Rahman , Fred C. Sabernick , Jeff A. Sprouse , Martin J. Grosz , Peter Fu , Russell M. Rector
IPC分类号： G06F15/177 , G06F9/445 , G06F9/48 , G06F11/16 , G06F11/20 , G06F11/22 , G06F12/02 , G06F12/08 , G06F13/24 , G06F13/36 , G06F9/46 , G06F13/14
CPC分类号： G06F11/1654 , G06F11/1637 , G06F11/22 , G06F12/0223 , G06F12/0862 , G06F9/4403 , G06F2212/6022
摘要： A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip. The maintenance diagnostic chip includes logic to halt either of the microprocessors if an error is detected, and read out the state of the microprocessors and a secondary cache attached to the microprocessors, before the state of the microprocessors at the time of the fault changes to a different state which might hide evidence of the cause of the fault.

5. 发明授权

US08711849B2 Output queued switch with a parallel shared memory, and method of operating same 失效
标题翻译：具有并行共享存储器的输出排队交换机及其操作方法
公开(公告)号：US08711849B2
公开(公告)日：2014-04-29
申请号：US12946780
申请日：2010-11-15
申请人： Kai-Yeung (Sunny) Siu , Brian Hang Wai Yang , Mizanur M. Rahman
发明人： Kai-Yeung (Sunny) Siu , Brian Hang Wai Yang , Mizanur M. Rahman
IPC分类号： H04L12/50 , H04Q3/68
CPC分类号： H04Q3/68 , H04L12/5601 , H04L49/108 , H04L49/153 , H04L49/60 , H04L49/606 , H04L2012/5627 , H04L2012/5651 , H04L2012/5681
摘要： A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node.
摘要翻译：网络交换机包括用于接收具有一组单元的数据流的输入层。每个小区包括指定目的地设备的数据和报头。输入层包括一组输入层电路。该组输入层电路的选定输入层电路接收数据流。所选择的输入层电路包括与一组目的地设备相对应的一组队列。所选择的输入层电路被配置为将所选择的单元从数据流分配给该组队列的选定队列。所选择的队列对应于由所选小区的头部指定的所选目的地设备。中间层包括一组中间层电路，每个中间层电路具有与该组目标设备相对应的一组缓冲器。所述一组中间层电路的所选择的中间层电路接收所选择的单元并将所选择的单元分配给与所选择的目的地设备相对应的选定缓冲器。输出层包括与目标设备组对应的一组输出层电路。所述一组输出层电路的所选输出层电路在将所选择的单元路由选定的输出层电路输出节点之前存储所选择的单元。

6. 发明授权

US07536631B1 Advanced communication apparatus and method for verified communication 失效
标题翻译：用于验证通信的高级通信装置和方法
公开(公告)号：US07536631B1
公开(公告)日：2009-05-19
申请号：US10452229
申请日：2003-06-03
申请人： Brian Hang Wai Yang , Kai-Yeung Siu , Mizanur M. Rahman , Ken Yeung , Hsi-Tung Huang
发明人： Brian Hang Wai Yang , Kai-Yeung Siu , Mizanur M. Rahman , Ken Yeung , Hsi-Tung Huang
IPC分类号： G06F11/08 , H03M13/00 , H04L1/00
CPC分类号： H03M13/13 , H03M13/3761 , H04L1/004 , H04L1/22
摘要： A communication circuit for verified communication comprising a transmitter having input terminals to receive a data word, an encoder configured to encode the data word to create an encoded word different from the data word, and output terminals configured to transmit the data word and the encoded word. A receiver is coupled to the transmitter and includes input terminals to receive the data word as a received word and the encoded word, a decoder configured to decode the encoded word to create a decoded word, and a comparator configured to compare the received word and the decoded word to create a select signal, and a selector responsive to the select signal and configured to select the received data word or the decoded word based at least in part on the select signal. Advantages of the invention include the ability to verify redundant received data without decreasing bandwidth or increasing latency.
摘要翻译：一种用于验证通信的通信电路，包括具有用于接收数据字的输入端的发送器，被配置为对数据字进行编码以创建与数据字不同的编码字的编码器，以及被配置为发送数据字和编码字的输出端。接收机耦合到发射机，并且包括用于接收数据字作为接收字和编码字的输入端，被配置为解码编码字以产生解码字的解码器，以及比较器，被配置为将接收到的字与解码字以产生选择信号，以及选择器，其响应于所述选择信号，并且被配置为至少部分地基于所述选择信号来选择所接收的数据字或所述解码字。本发明的优点包括在不减少带宽或增加延迟的情况下验证冗余接收数据的能力。

7. 发明授权

US07835334B2 Output queued switch with a parallel shared memory, and method of operating same 有权
标题翻译：具有并行共享存储器的输出排队交换机及其操作方法
公开(公告)号：US07835334B2
公开(公告)日：2010-11-16
申请号：US12198776
申请日：2008-08-26
申请人： Kai-Yeung (Sunny) Siu , Brain Hang Wai Yang , Mizanur M. Rahman
发明人： Kai-Yeung (Sunny) Siu , Brain Hang Wai Yang , Mizanur M. Rahman
IPC分类号： H04W4/00
CPC分类号： H04Q3/68 , H04L12/5601 , H04L49/108 , H04L49/153 , H04L49/60 , H04L49/606 , H04L2012/5627 , H04L2012/5651 , H04L2012/5681
摘要： A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node.
摘要翻译：网络交换机包括用于接收具有一组单元的数据流的输入层。每个小区包括指定目的地设备的数据和报头。输入层包括一组输入层电路。该组输入层电路的选定输入层电路接收数据流。所选择的输入层电路包括与一组目的地设备相对应的一组队列。所选择的输入层电路被配置为将所选择的单元从数据流分配给该组队列的选定队列。所选择的队列对应于由所选小区的头部指定的所选目的地设备。中间层包括一组中间层电路，每个中间层电路具有与该组目标设备相对应的一组缓冲器。所述一组中间层电路的所选择的中间层电路接收所选择的单元并将所选择的单元分配给与所选择的目的地设备相对应的选定缓冲器。输出层包括与目标设备组对应的一组输出层电路。所述一组输出层电路的所选输出层电路在将所选择的单元路由选定的输出层电路输出节点之前存储所选择的单元。

8. 发明申请

US20080310418A1 OUTPUT QUEUED SWITCH WITH A PARALLEL SHARED MEMORY, AND METHOD OF OPERATING SAME 有权
标题翻译：具有并行共享存储器的输出QUEUED开关及其操作方法
公开(公告)号：US20080310418A1
公开(公告)日：2008-12-18
申请号：US12198776
申请日：2008-08-26
申请人： Kai-Yeung (Sunny) Siu , Brain Hang Wai Yang , Mizanur M. Rahman
发明人： Kai-Yeung (Sunny) Siu , Brain Hang Wai Yang , Mizanur M. Rahman
IPC分类号： H04L12/56
CPC分类号： H04Q3/68 , H04L12/5601 , H04L49/108 , H04L49/153 , H04L49/60 , H04L49/606 , H04L2012/5627 , H04L2012/5651 , H04L2012/5681
摘要： A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node.
摘要翻译：网络交换机包括用于接收具有一组单元的数据流的输入层。每个小区包括指定目的地设备的数据和报头。输入层包括一组输入层电路。该组输入层电路的选定输入层电路接收数据流。所选择的输入层电路包括与一组目的地设备相对应的一组队列。所选择的输入层电路被配置为将所选择的单元从数据流分配给该组队列的选定队列。所选择的队列对应于由所选小区的头部指定的所选目的地设备。中间层包括一组中间层电路，每个中间层电路具有与该组目标设备相对应的一组缓冲器。所述一组中间层电路的所选择的中间层电路接收所选择的单元并将所选择的单元分配给与所选择的目的地设备相对应的选定缓冲器。输出层包括与目标设备组对应的一组输出层电路。所述一组输出层电路的所选输出层电路在将所选择的单元路由选定的输出层电路输出节点之前存储所选择的单元。

9. 发明授权

US07420969B2 Network switch with a parallel shared memory 失效
标题翻译：具有并行共享存储器的网络交换机
公开(公告)号：US07420969B2
公开(公告)日：2008-09-02
申请号：US09939454
申请日：2001-08-24
申请人： Kai-Yeung (Sunny) Siu , Brain Hang Wai Yang , Mizanur M. Rahman
发明人： Kai-Yeung (Sunny) Siu , Brain Hang Wai Yang , Mizanur M. Rahman
IPC分类号： H04L12/50
CPC分类号： H04Q3/68 , H04L12/5601 , H04L49/108 , H04L49/153 , H04L49/60 , H04L49/606 , H04L2012/5627 , H04L2012/5651 , H04L2012/5681
摘要： A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node.
摘要翻译：网络交换机包括用于接收具有一组单元的数据流的输入层。每个小区包括指定目的地设备的数据和报头。输入层包括一组输入层电路。该组输入层电路的选定输入层电路接收数据流。所选择的输入层电路包括与一组目的地设备相对应的一组队列。所选择的输入层电路被配置为将所选择的单元从数据流分配给该组队列的选定队列。所选择的队列对应于由所选小区的头部指定的所选目的地设备。中间层包括一组中间层电路，每个中间层电路具有与该组目标设备相对应的一组缓冲器。所述一组中间层电路的所选择的中间层电路接收所选择的单元并将所选择的单元分配给与所选择的目的地设备相对应的选定缓冲器。输出层包括与目标设备组对应的一组输出层电路。所述一组输出层电路的所选输出层电路在将所选择的单元路由选定的输出层电路输出节点之前存储所选择的单元。

10. 发明授权

US07046681B2 Network switch for routing network traffic 失效
标题翻译：用于路由网络流量的网络交换机
公开(公告)号：US07046681B2
公开(公告)日：2006-05-16
申请号：US09940148
申请日：2001-08-24
申请人： Kai-Yeung (Sunny) Siu , Brain Hang Wai Yang , Mizanur M. Rahman
发明人： Kai-Yeung (Sunny) Siu , Brain Hang Wai Yang , Mizanur M. Rahman
IPC分类号： H04L12/28
CPC分类号： H04L49/101 , H04L49/106 , H04L49/205 , H04L49/3045 , H04L49/60 , H04L49/606 , H04L2012/5651 , H04L2012/5667
摘要： A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node.
摘要翻译：网络交换机包括用于接收具有一组单元的数据流的输入层。每个小区包括指定目的地设备的数据和报头。输入层包括一组输入层电路。该组输入层电路的选定输入层电路接收数据流。所选择的输入层电路包括与一组目的地设备相对应的一组队列。所选择的输入层电路被配置为将所选择的单元从数据流分配给该组队列的选定队列。所选择的队列对应于由所选小区的头部指定的所选目的地设备。中间层包括一组中间层电路，每个中间层电路具有与该组目标设备相对应的一组缓冲器。所述一组中间层电路的所选择的中间层电路接收所选择的单元并将所选择的单元分配给与所选择的目的地设备相对应的选定缓冲器。输出层包括与目标设备组对应的一组输出层电路。所述一组输出层电路的所选输出层电路在将所选择的单元路由选定的输出层电路输出节点之前存储所选择的单元。

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