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1. 发明授权

US08737156B2 Mapping between two buses using serial addressing bits 有权
标题翻译：使用串行寻址位在两条总线之间进行映射
公开(公告)号：US08737156B2
公开(公告)日：2014-05-27
申请号：US13656758
申请日：2012-10-22
申请人： Ching-Min Hou
发明人： Ching-Min Hou
IPC分类号： G11C8/10 , G11C8/12 , G06F12/00 , G06F12/02
CPC分类号： G11C8/10 , G06F12/00 , G06F12/02 , G11C8/12 , G11C16/08
摘要： A solution is provided to flexibly choose a combination of flash memory devices to reduce the overall cost of the flash memory devices or increase the overall utilization of the flash memory devices, while satisfying the capacity requirements for the flash memory devices in a system design, wherein a decoding unit is used for determining which flash memory devices will be accessed and re-mapping incoming serial addressing bits, for accessing one flash memory device, into an outgoing serial addressing bits for accessing another flash memory device.
摘要翻译：提供了一种解决方案，以灵活地选择闪存设备的组合，以降低闪存设备的整体成本或增加闪存设备的整体利用率，同时满足系统设计中闪存设备的容量要求，其中解码单元用于确定哪些闪存设备将被访问，并将用于访问一个闪速存储器设备的输入串行寻址位重新映射成用于访问另一个闪存设备的输出串行寻址位。

2. 发明申请

US20130100736A1 MAPPING BETWEEN TWO BUSES USING SERIAL ADDRESSING BITS 有权
标题翻译：使用串行寻址位置的两个总线之间的映射
公开(公告)号：US20130100736A1
公开(公告)日：2013-04-25
申请号：US13656758
申请日：2012-10-22
申请人： Ching-Min Hou
发明人： Ching-Min Hou
IPC分类号： G11C16/08
CPC分类号： G11C8/10 , G06F12/00 , G06F12/02 , G11C8/12 , G11C16/08
摘要： A solution is provided to flexibly choose a combination of flash memory devices to reduce the overall cost of the flash memory devices or increase the overall utilization of the flash memory devices, while satisfying the capacity requirements for the flash memory devices in a system design, wherein a decoding unit is used for determining which flash memory devices will be accessed and re-mapping incoming serial addressing bits, for accessing one flash memory device, into an outgoing serial addressing bits for accessing another flash memory device.
摘要翻译：提供了一种解决方案，以灵活地选择闪存设备的组合，以降低闪存设备的整体成本或增加闪存设备的整体利用率，同时满足系统设计中闪存设备的容量要求，其中解码单元用于确定哪些闪存设备将被访问，并将用于访问一个闪速存储器设备的输入串行寻址位重新映射成用于访问另一个闪存设备的输出串行寻址位。

3. 发明授权

US08301846B2 Integrated memory control apparatus 失效
标题翻译：集成式存储器控制装置
公开(公告)号：US08301846B2
公开(公告)日：2012-10-30
申请号：US13163747
申请日：2011-06-20
申请人： Ching-Min Hou
发明人： Ching-Min Hou
IPC分类号： G06F12/00
CPC分类号： G06F13/4027
摘要： An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.
摘要翻译：提供一种包括第一接口解码器，第二接口解码器和接口控制器的集成存储器控制装置。其中，第一接口解码器通过第一串行外围接口（SPI）耦合到控制芯片，第二接口解码器通过通用传输接口耦合到微处理器单元，并且接口控制器通过第二个SPI。当接口控制器从控制芯片和微处理器单元接收到请求信号时，控制芯片可以通过第一和第二SPI从存储器中正确读取数据。另一方面，微处理器单元可以通过通用传输接口停止从存储器读取数据。因此，控制芯片和微处理器单元可以共享相同的存储器。

4. 发明授权

US08024540B2 Integrated memory control apparatus 有权
标题翻译：集成式存储器控制装置
公开(公告)号：US08024540B2
公开(公告)日：2011-09-20
申请号：US12814489
申请日：2010-06-14
申请人： Ching-Min Hou
发明人： Ching-Min Hou
IPC分类号： G06F12/00
CPC分类号： G06F13/4027
摘要： An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.
摘要翻译：提供一种包括第一接口解码器，第二接口解码器和接口控制器的集成存储器控制装置。其中，第一接口解码器通过第一串行外围接口（SPI）耦合到控制芯片，第二接口解码器通过通用传输接口耦合到微处理器单元，并且接口控制器通过第二个SPI。当接口控制器从控制芯片和微处理器单元接收到请求信号时，控制芯片可以通过第一和第二SPI从存储器中正确读取数据。另一方面，微处理器单元可以通过通用传输接口停止从存储器读取数据。因此，控制芯片和微处理器单元可以共享相同的存储器。

5. 发明授权

US07818529B2 Integrated memory control apparatus 有权
标题翻译：集成式存储器控制装置
公开(公告)号：US07818529B2
公开(公告)日：2010-10-19
申请号：US11941983
申请日：2007-11-19
申请人： Ching-Min Hou
发明人： Ching-Min Hou
IPC分类号： G06F12/00
CPC分类号： G06F13/4027
摘要： An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.
摘要翻译：提供一种包括第一接口解码器，第二接口解码器和接口控制器的集成存储器控制装置。其中，第一接口解码器通过第一串行外围接口（SPI）耦合到控制芯片，第二接口解码器通过通用传输接口耦合到微处理器单元，并且接口控制器通过第二个SPI。当接口控制器从控制芯片和微处理器单元接收到请求信号时，控制芯片可以通过第一和第二SPI从存储器中正确读取数据。另一方面，微处理器单元可以通过通用传输接口停止从存储器读取数据。因此，控制芯片和微处理器单元可以共享相同的存储器。

6. 发明授权

US07685343B2 Data access method for serial bus 有权
标题翻译：串行总线的数据访问方法
公开(公告)号：US07685343B2
公开(公告)日：2010-03-23
申请号：US11692932
申请日：2007-03-29
申请人： Ching-Min Hou , Kung-Hsien Chu
发明人： Ching-Min Hou , Kung-Hsien Chu
IPC分类号： G06F13/00
CPC分类号： G06F13/4291
摘要： A data access method for serial bus is provided. During a write/read cycle, the write/read cycle is divided into a plurality of transmitting intervals and a plurality of suspending intervals. In each of the transmitting intervals, a clock signal is transmitted on a clock pin and a data signal is transmitted on a data pin. In each of the suspending intervals, the clock signal stop being transmitted on the clock pin. In other words, the present invention uses an interrupted clock signal, such that an embedded controller can directly write a received data in a flash memory or directly output the data read from the flash memory, so as to avoid using a plurality of registers. Therefore, the present invention can decrease the cost of the embedded controller and reduce the area of the integrated circuit.
摘要翻译：提供串行总线的数据访问方法。在写/读周期期间，写/读周期被分成多个发送间隔和多个暂停间隔。在每个发送间隔中，在时钟引脚上发送时钟信号，并且在数据引脚上发送数据信号。在每个暂停间隔中，时钟信号停止在时钟引脚上传输。换句话说，本发明使用中断的时钟信号，使得嵌入式控制器可以直接将接收到的数据写入闪速存储器中或者直接输出从闪速存储器读取的数据，以避免使用多个寄存器。因此，本发明可以降低嵌入式控制器的成本并减小集成电路的面积。

7. 外观设计

USD578621S1 Toilet 有权
标题翻译：厕所
公开(公告)号：USD578621S1
公开(公告)日：2008-10-14
申请号：US29299146
申请日：2007-12-20
申请人： Jennifer Lee , Li-Min Hou
设计人： Jennifer Lee , Li-Min Hou

8. 外观设计

USD578620S1 Toilet 有权
公开(公告)号：USD578620S1
公开(公告)日：2008-10-14
申请号：US29299145
申请日：2007-12-20
申请人： Qiong Zou , Li-Min Hou
设计人： Qiong Zou , Li-Min Hou

9. 发明申请

US20080122659A1 EMBEDDED CONTROLLER AND COMPUTER SYSTEM USING THE SAME 审中-公开
标题翻译：嵌入式控制器和使用该控制器的计算机系统
公开(公告)号：US20080122659A1
公开(公告)日：2008-05-29
申请号：US11672966
申请日：2007-02-09
申请人： Ching-Min Hou , Po-Cheng Chen
发明人： Ching-Min Hou , Po-Cheng Chen
IPC分类号： H03K17/94
CPC分类号： G06F3/023
摘要： An embedded controller includes a keyboard interface, a keyboard signal conversion unit, a flash memory control unit, and a selection unit. When the selection unit couples the flash memory control unit to the keyboard interface according to an indication signal, a remote controller is coupled to the keyboard interface so as to input an input signal to the embedded controller through the keyboard interface. And the flash memory control unit decodes the input signal and writes it into a flash memory to change a data stored in the flash memory.
摘要翻译：嵌入式控制器包括键盘接口，键盘信号转换单元，闪存控制单元和选择单元。当选择单元根据指示信号将闪存控制单元耦合到键盘接口时，遥控器耦合到键盘接口，以通过键盘接口将输入信号输入到嵌入式控制器。并且闪速存储器控制单元解码输入信号并将其写入闪速存储器以改变存储在闪速存储器中的数据。

10. 发明申请

US20130151832A1 FLASH MEMORY STORAGE SYSTEM AND DATA PROTECTION METHOD THEREOF 审中-公开
标题翻译：闪存存储系统及其数据保护方法
公开(公告)号：US20130151832A1
公开(公告)日：2013-06-13
申请号：US13368341
申请日：2012-02-08
申请人： Chia-Yuan Chou , Ching-Min Hou
发明人： Chia-Yuan Chou , Ching-Min Hou
IPC分类号： G06F15/177
CPC分类号： G06F12/1433 , G06F2212/2022
摘要： A flash memory storage system includes a flash memory, a host and a controller is provided. The controller couples to the host and the flash memory, and restricts the host to access the flash memory according to a state of the host. When the host is in a booting state or in a resetting state, the controller allows the host to access the flash memory. After the host completes a booting process or a resetting process, the controller restricts the host to access the flash memory so as to protect a data stored by the flash memory. Besides, a data protection method for which applied to the above-mentioned storage system is also provided in the present invention.
摘要翻译：闪存存储系统包括闪存，主机和控制器。控制器耦合到主机和闪存，并根据主机的状态来限制主机访问闪存。当主机处于启动状态或处于重置状态时，控制器允许主机访问闪存。在主机完成引导过程或重置过程之后，控制器限制主机访问闪存，以保护闪存存储的数据。此外，在本发明中还提供了应用于上述存储系统的数据保护方法。

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