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1. 发明授权

US08525386B2 Dynamically adjustable orthotic device 有权
标题翻译：动态调节矫正装置
公开(公告)号：US08525386B2
公开(公告)日：2013-09-03
申请号：US12634263
申请日：2009-12-09
申请人： Sylvia D. Pas , Michael F. Pas
发明人： Sylvia D. Pas , Michael F. Pas
IPC分类号： H01L41/09 , H01L41/107 , H01L41/113 , H01L41/18
CPC分类号： A61B5/11 , A61B5/1036 , A61B5/6807 , A61F5/14 , B29L2031/50 , H01L41/113
摘要： An orthotic device comprises a flexible support structure comprising at least one surface for contacting a body part of a user, a plurality of pressure sensors configured for coupling to a microcontroller, and a plurality of displacement regions. Each region defines a portion of said flexible support structure, wherein each portion includes at least one sensor disposed on or below the at least one surface and at least one electrically deformable unit. Each unit comprises at least one electroactive material and is configured for coupling to the microcontroller and to a power source. The device is dynamically adjustable to change its shape and support properties, when an electrical voltage is applied to the electroactive material under the control of a microcontroller.
摘要翻译：矫正装置包括柔性支撑结构，其包括至少一个用于接触使用者的身体部分的表面，配置成耦合到微控制器的多个压力传感器和多个位移区域。每个区域限定所述柔性支撑结构的一部分，其中每个部分包括设置在所述至少一个表面上或下方的至少一个传感器和至少一个电可变形单元。每个单元包括至少一个电活性材料，并且被配置为耦合到微控制器和电源。当在微控制器的控制下将电压施加到电活性材料时，该装置可动态地调节以改变其形状和支持性质。

2. 发明授权

US08304333B2 Method of forming a high-k gate dielectric layer 有权
标题翻译：形成高k栅介质层的方法
公开(公告)号：US08304333B2
公开(公告)日：2012-11-06
申请号：US12886863
申请日：2010-09-21
申请人： Manfred Ramin , Michael F. Pas , Husam Alshareef
发明人： Manfred Ramin , Michael F. Pas , Husam Alshareef
IPC分类号： H01L21/3205 , H01L21/8238
CPC分类号： H01L21/02321 , H01L21/02156 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28176 , H01L21/28185 , H01L21/28202 , H01L21/31155 , H01L21/3144 , H01L21/823462 , H01L21/823857
摘要： A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer.
摘要翻译：一种制造半导体器件的方法包括在栅极电介质上形成栅电极。通过在氮化硅氧化物层上形成镧系元素金属层，然后对扩散原子进行退火以形成镧系元素氧氮化硅层来形成栅极电介质。可以在退火之前或之后沉积栅极电极层。在一个实施例中，栅极电极层包括非镧系元素金属层，形成在非镧系元素金属层上的阻挡层和形成在阻挡层上的多晶硅层。可以将铪原子任选地注入到氮化硅氧化物层中。

3. 发明申请

US20090127632A1 Semiconductor Device Manufactured by Removing Sidewalls During Replacement Gate Integration Scheme 有权
标题翻译：半导体器件通过在替换门集成方案中去除侧壁制造
公开(公告)号：US20090127632A1
公开(公告)日：2009-05-21
申请号：US11943106
申请日：2007-11-20
申请人： Michael F. Pas
发明人： Michael F. Pas
IPC分类号： H01L29/78 , H01L21/8236
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/823864 , H01L29/4958 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor substrate, wherein the gate electrodes are free of spacer sidewalls. The device further includes source/drains having source/drain extensions associated therewith, located in the semiconductor substrate and adjacent each of the gate electrodes. A first pre-metal dielectric layer is located on the sidewalls of the gate electrodes and over the source/drains, and a second pre-metal dielectric layer is located on the first pre-metal dielectric layer. Contact plugs extend through the first and second pre-metal dielectric layers.
摘要翻译：本发明的一个方面提供了一种半导体器件，其包括位于半导体衬底之上的包括金属或金属合金的栅电极，其中栅电极没有间隔壁。该器件还包括源极/漏极，其源极/漏极延伸部与其相关联，位于半导体衬底中并与每个栅电极相邻。第一预金属介电层位于栅电极的侧壁上和源极/漏极之上，第二预金属介电层位于第一预金属介电层上。接触塞延伸穿过第一和第二预金属介电层。

4. 发明授权

US08409943B2 Work function adjustment with the implant of lanthanides 有权
标题翻译：用镧系元素植入功能调整功能
公开(公告)号：US08409943B2
公开(公告)日：2013-04-02
申请号：US12979908
申请日：2010-12-28
申请人： Manfred Ramin , Michael F. Pas , Husam Alshareef
发明人： Manfred Ramin , Michael F. Pas , Husam Alshareef
IPC分类号： H01L21/336
CPC分类号： H01L21/28008 , H01L21/265 , H01L21/28097 , H01L21/28176 , H01L21/28194 , H01L21/823842 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.
摘要翻译：提供半导体器件和制造方法，其中提供完全硅化的栅极。在硅化之前将镧系金属注入栅极电极层，并在激活退火期间扩散到栅极电介质中。该过程和结果结构提供了栅电极功函数的调整，从而调谐所得晶体管的阈值电压。

5. 发明授权

US07799669B2 Method of forming a high-k gate dielectric layer 有权
标题翻译：形成高k栅介质层的方法
公开(公告)号：US07799669B2
公开(公告)日：2010-09-21
申请号：US11741476
申请日：2007-04-27
申请人： Manfred Ramin , Michael F. Pas , Husam Alshareef
发明人： Manfred Ramin , Michael F. Pas , Husam Alshareef
IPC分类号： H01L21/3205 , H01L21/8238
CPC分类号： H01L21/02321 , H01L21/02156 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28176 , H01L21/28185 , H01L21/28202 , H01L21/31155 , H01L21/3144 , H01L21/823462 , H01L21/823857
摘要： A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon oxide layer on a semiconductor substrate, nitridating the silicon oxide layer to form a nitrided silicon oxide layer and incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer.
摘要翻译：一种半导体器件的制造方法。该方法包括形成电介质层。形成电介质层包括在半导体衬底上沉积氧化硅层，氮化氧化硅层以形成氮化氧化硅层，并将镧系元素原子掺入到氮化硅氧化物层中以形成镧系元素氧氮化硅层。

6. 发明授权

US07795097B2 Semiconductor device manufactured by removing sidewalls during replacement gate integration scheme 有权
标题翻译：在替换栅极集成方案中通过去除侧壁制造的半导体器件
公开(公告)号：US07795097B2
公开(公告)日：2010-09-14
申请号：US11943106
申请日：2007-11-20
申请人： Michael F. Pas
发明人： Michael F. Pas
IPC分类号： H01L21/8236
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/823864 , H01L29/4958 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor substrate, wherein the gate electrodes are free of spacer sidewalls. The device further includes source/drains having source/drain extensions associated therewith, located in the semiconductor substrate and adjacent each of the gate electrodes. A first pre-metal dielectric layer is located on the sidewalls of the gate electrodes and over the source/drains, and a second pre-metal dielectric layer is located on the first pre-metal dielectric layer. Contact plugs extend through the first and second pre-metal dielectric layers.
摘要翻译：本发明的一个方面提供了一种半导体器件，其包括位于半导体衬底之上的包括金属或金属合金的栅电极，其中栅电极没有间隔壁。该器件还包括源极/漏极，其源极/漏极延伸部与其相关联，位于半导体衬底中并与每个栅电极相邻。第一预金属介电层位于栅电极的侧壁上以及源极/漏极之上，第二预金属介电层位于第一预金属介电层上。接触塞延伸穿过第一和第二预金属介电层。

7. 发明授权

US07642153B2 Methods for forming gate electrodes for integrated circuits 有权
标题翻译：用于形成用于集成电路的栅电极的方法
公开(公告)号：US07642153B2
公开(公告)日：2010-01-05
申请号：US11877175
申请日：2007-10-23
申请人： Michael F. Pas
发明人： Michael F. Pas
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823835 , H01L29/785
摘要： A method of forming an integrated circuit can include the steps of providing a substrate having a semiconducting surface and forming a plurality of semiconducting multilayer features on the substrate surface, the features comprising a base layer and a compositionally different capping layer on the base layer. The method can also include forming spacers on sidewalls of the plurality of features, etching the capping layer, where the etching comprises selectively removing the capping layer, removing at least a portion of the base layer to form a plurality of trenches, and forming gate electrodes in the trenches.
摘要翻译：形成集成电路的方法可以包括以下步骤：提供具有半导体表面的衬底，并在衬底表面上形成多个半导体多层结构，其特征包括在基底层上的基底层和组成上不同的覆盖层。该方法还可以包括在多个特征的侧壁上形成间隔物，蚀刻覆盖层，其中蚀刻包括选择性地去除覆盖层，去除基底层的至少一部分以形成多个沟槽，以及形成栅电极在壕沟里

8. 发明申请

US20080261368A1 WORK FUNCTION ADJUSTMENT WITH THE IMPLANT OF LANTHANIDES 有权
标题翻译：工作功能调整与植物的植被
公开(公告)号：US20080261368A1
公开(公告)日：2008-10-23
申请号：US11737856
申请日：2007-04-20
申请人： Manfred Ramin , Michael F. Pas , Husam Alshareef
发明人： Manfred Ramin , Michael F. Pas , Husam Alshareef
IPC分类号： H01L21/336
CPC分类号： H01L21/28008 , H01L21/265 , H01L21/28097 , H01L21/28176 , H01L21/28194 , H01L21/823842 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.
摘要翻译：提供半导体器件和制造方法，其中为MOS晶体管提供完全硅化的晶体管栅极。在硅化之前将镧系金属注入栅极电极层，并在激活退火期间扩散到栅极电介质中。该过程和结果结构提供了栅电极功函数的调整，从而调谐所得晶体管的阈值电压。

9. 发明申请

US20080160736A1 Lanthanide series metal implant to control work function of metal gate electrodes 有权
标题翻译：镧系金属植入物，用于控制金属栅电极的功能
公开(公告)号：US20080160736A1
公开(公告)日：2008-07-03
申请号：US11700278
申请日：2007-01-31
申请人： Husam Alshareef , Manfred Ramin , Michael F. Pas
发明人： Husam Alshareef , Manfred Ramin , Michael F. Pas
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823857 , H01L21/823842
摘要： Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal nitride is formed above a gate dielectric. A lanthaide series metal is implanted into the metal screen layer above the gate dielectric. The lanthaide metal is contained in the screen layer or at the interface between the screen metal layer and the gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.
摘要翻译：提供了半导体器件和制造方法，其中为MOS晶体管提供金属晶体管栅极。在栅极电介质上形成金属氮化物。将兰花系列金属注入到栅极电介质上方的金属屏蔽层中。蓝色金属包含在屏幕层中或屏幕金属层和栅极电介质之间的界面处。该过程提供了栅电极功函数的调整，从而调谐所得PMOS或NMOS晶体管的阈值电压。

10. 发明授权

US6054684A Ultra fast temperature ramp up and down in a furnace using interleaving shutters 失效
标题翻译：使用交错百叶窗在炉内上下高速升温
公开(公告)号：US6054684A
公开(公告)日：2000-04-25
申请号：US964515
申请日：1997-11-05
申请人： Michael F. Pas , C. Rinn Cleavelin , Sylvia D. Pas
发明人： Michael F. Pas , C. Rinn Cleavelin , Sylvia D. Pas
IPC分类号： H01L21/22 , C30B31/12 , H01L21/324 , F27B5/14
CPC分类号： C30B31/12
摘要： One embodiment of the instant invention is a process chamber for heating a semiconductor wafer, the process chamber comprising: heating elements (elements 104 of FIG. 2a) for providing heating energy; means for holding (means 112 of FIG. 2a) the semiconductor wafer; and shutters situated between the heating elements and the means for holding the semiconductor wafer, the shutters (shutters 108 of FIGS. 2a and 2b and shutters of FIGS. 2c and 2d for blocking the heating energy from getting to the semiconductor wafer when the shutters are in a closed position and for directing the heating energy to the semiconductor wafer when in an open position. Preferably, the shutters are comprised of: an outer surface which is coated with a material which reflects the heating energy back towards the heating elements when the shutters are in the closed position; an inner surface which faces the means for holding the semiconductor wafer when the shutters are in the dosed position; an axis which the shutters revolve around so as to open and close; and an insulating material situated between the inner and outer surfaces.
摘要翻译：本发明的一个实施例是用于加热半导体晶片的处理室，所述处理室包括：加热元件（图2a的元件104），用于提供加热能量; 用于保持（图2a的装置112）半导体晶片的装置; 和位于加热元件和用于保持半导体晶片的装置之间的快门，快门（图2a和2b的快门108和图2c和2d的快门，用于当快门为快门时阻止加热能量进入半导体晶片在闭合位置，并且当处于打开位置时将加热能量引导到半导体晶片。优选地，快门由以下部件构成：外表面涂覆有当快门反射加热能量时朝向加热元件反射的材料处于关闭位置;当快门处于计量位置时面对用于保持半导体晶片的装置的内表面;快门围绕着开启和关闭的轴线;以及绝缘材料，位于内部和外表面。

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