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1. 发明授权

US09129060B2 QoS based dynamic execution engine selection 有权
标题翻译：基于QoS的动态执行引擎选择
公开(公告)号：US09129060B2
公开(公告)日：2015-09-08
申请号：US13272975
申请日：2011-10-13
申请人： Najeeb I. Ansari , Michael Carns , Jeffrey Schroeder , Bryan Chin
发明人： Najeeb I. Ansari , Michael Carns , Jeffrey Schroeder , Bryan Chin
IPC分类号： G06F9/50 , G06F13/362
CPC分类号： G06F9/30181 , G06F9/30 , G06F9/30145 , G06F9/38 , G06F9/3836 , G06F9/3851 , G06F9/50 , G06F9/5044 , G06F13/362
摘要： In one embodiment, a processor includes plural processing cores, and plural instruction stores, each instruction store storing at least one instruction, each instruction having a corresponding group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having a plurality of group execution masks and a store execution matrix comprising a plurality of store execution masks. The processor further includes a core selection unit that, for each instruction within each instruction store, selects a store execution mask from the store execution matrix. The core selection unit for each instruction within each instruction store selects at least one group execution mask from the group execution matrix. The core selection unit performs logic operations to create a core request mask. The processor includes an arbitration unit that determines instruction priority among each instruction, assigns an instruction for each available core, and signals the instruction store.
摘要翻译：在一个实施例中，处理器包括多个处理核心和多个指令存储器，每个指令存储器存储至少一个指令，每个指令具有对应的组号，每个指令存储器具有唯一的标识符。处理器还包括具有多个组执行掩码的组执行矩阵和包括多个存储执行掩码的存储执行矩阵。处理器还包括核心选择单元，对于每个指令存储器中的每个指令，从存储执行矩阵中选择存储执行掩码。每个指令存储器中的每个指令的核心选择单元从组执行矩阵中选择至少一个组执行掩码。核心选择单元执行逻辑操作以创建核心请求掩码。处理器包括确定每个指令之间的指令优先级的仲裁单元，为每个可用的核心分配指令，并向指令存储器发出信号。

2. 发明授权

US09128769B2 Processor with dedicated virtual functions and dynamic assignment of functional resources 有权
标题翻译：具有专用虚拟功能和动态分配功能资源的处理器
公开(公告)号：US09128769B2
公开(公告)日：2015-09-08
申请号：US13272937
申请日：2011-10-13
申请人： Jeffrey Schroeder , Jeff Pangborn , Najeeb Ansari , Bryan Chin , Leo Chen , Ahmed Shahid , Paul Scrobohaci , Chee Hu , Michael Carns , Wu Ye , Brian Hunter
发明人： Jeffrey Schroeder , Jeff Pangborn , Najeeb Ansari , Bryan Chin , Leo Chen , Ahmed Shahid , Paul Scrobohaci , Chee Hu , Michael Carns , Wu Ye , Brian Hunter
IPC分类号： G06F9/46 , G06F9/50
CPC分类号： G06F9/5077
摘要： In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to dispatch work from any work store corresponding to any virtual function or physical function to any released hardware resources.
摘要翻译：在一个实施例中，处理器包括多个硬件资源，每个硬件资源具有时钟周期。如果处理器的模式被设置为虚拟功能模式，则处理器还包括多个工作存储，每个工作存储被分配到多个虚拟功能中的一个，并且如果分配给一个物理功能的模式处理器设置为物理功能模式。所述处理器还包括配置逻辑，所述调度逻辑被配置为将对应于任何虚拟功能或物理功能的任何工作存储器的工作分配给任何已发布的硬件资源。

3. 发明申请

US20130097598A1 PROCESSOR WITH DEDICATED VIRTUAL FUNCTIONS AND DYNAMIC ASSIGNMENT OF FUNCTIONAL RESOURCES 有权
标题翻译：具有专属虚拟功能的处理器和功能资源的动态分配
公开(公告)号：US20130097598A1
公开(公告)日：2013-04-18
申请号：US13272937
申请日：2011-10-13
申请人： Jeffrey Schroeder , Jeff Pangborn , Najeeb Ansari , Bryan Chin , Leo Chen , Ahmed Shahid , Paul Scrobohaci , Chee Hu , Michael Carns , Wu Ye , Brian Hunter
发明人： Jeffrey Schroeder , Jeff Pangborn , Najeeb Ansari , Bryan Chin , Leo Chen , Ahmed Shahid , Paul Scrobohaci , Chee Hu , Michael Carns , Wu Ye , Brian Hunter
IPC分类号： G06F9/50
CPC分类号： G06F9/5077
摘要： In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to dispatch work from any work store corresponding to any virtual function or physical function to any released hardware resources.
摘要翻译：在一个实施例中，处理器包括多个硬件资源，每个硬件资源具有时钟周期。如果处理器的模式被设置为虚拟功能模式，则处理器还包括多个工作存储，每个工作存储被分配到多个虚拟功能中的一个，并且如果分配给一个物理功能的模式处理器设置为物理功能模式。所述处理器还包括配置逻辑，所述调度逻辑被配置为将对应于任何虚拟功能或物理功能的任何工作存储器的工作分配给任何已发布的硬件资源。

4. 发明申请

US20130097350A1 QOS BASED DYNAMIC EXECUTION ENGINE SELECTION 有权
标题翻译：基于QOS的动态执行发动机选择
公开(公告)号：US20130097350A1
公开(公告)日：2013-04-18
申请号：US13272975
申请日：2011-10-13
申请人： Najeeb I. Ansari , Michael Carns , Jeffrey Schroeder , Bryan Chin
发明人： Najeeb I. Ansari , Michael Carns , Jeffrey Schroeder , Bryan Chin
IPC分类号： G06F13/18
CPC分类号： G06F9/30181 , G06F9/30 , G06F9/30145 , G06F9/38 , G06F9/3836 , G06F9/3851 , G06F9/50 , G06F9/5044 , G06F13/362
摘要： In one embodiment, a processor includes processing cores, and instruction stores storing instructions at least one instructions having a group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having group execution masks and a store execution matrix having store execution masks. The processor further includes a core selection unit that, for each instruction, selects a store execution mask using the unique identifier as an index. The core selection unit for each instruction, selects at least one group execution mask using the group number as an index, and performs logic operations on the selected group execution mask and the store execution mask to create a core request mask. The processor also includes an arbitration unit that determines instruction priority, assigns an instruction for each available core, and signals the instruction store of the assigned instruction to send the assigned instruction to the available core.
摘要翻译：在一个实施例中，处理器包括处理核心，指令存储器存储具有组号码的至少一个指令，每个指令存储器具有唯一标识符。处理器还包括具有组执行掩码的组执行矩阵和具有存储执行掩码的存储执行矩阵。处理器还包括核心选择单元，对于每个指令，使用唯一标识符作为索引来选择存储执行掩码。每个指令的核心选择单元使用组号作为索引来选择至少一个组执行掩码，并对所选择的组执行掩码和存储执行掩码执行逻辑操作以创建核心请求掩码。该处理器还包括确定指令优先级的仲裁单元，为每个可用的核心分配一条指令，并且向指定的指令发送指令存储器以将分配的指令发送到可用的核心。

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