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1. 发明授权

US09529745B2 System on chip and method of operating a system on chip 有权
标题翻译：片上系统和芯片上系统的操作方法
公开(公告)号：US09529745B2
公开(公告)日：2016-12-27
申请号：US14190374
申请日：2014-02-26
申请人： Nir Atzmon , Ron-Michael Bar , Eran Glickman , Benny Michalovich
发明人： Nir Atzmon , Ron-Michael Bar , Eran Glickman , Benny Michalovich
IPC分类号： G06F13/16 , G06F13/38 , G06F13/32
CPC分类号： G06F13/1673 , G06F13/32
摘要： A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit. Each of the data sources is capable of providing a data stream. The memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer. Each of the buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer. The memory control unit is arranged to allocate and de-allocate memory regions to and from each of the buffers in dependence of the buffer characteristics of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers.A method of operating a system on chip is also described.
摘要翻译：还描述了一种操作片上系统的方法。

2. 发明申请

US20160012254A1 APPARATUS, A METHOD AND MACHINE READABLE INSTRUCTIONS FOR CONTROLLING PERFORMANCE OF A PROCESS IN RESPONSE TO A DETECTED PROCESSING EVENT 审中-公开
标题翻译：装置，方法和机器可读指令，用于控制处理对检测到的处理事件的响应的性能
公开(公告)号：US20160012254A1
公开(公告)日：2016-01-14
申请号：US14325843
申请日：2014-07-08
申请人： RON-MICHAEL BAR , ERAN GLICKMAN , AMIR DAVID MODAN
发明人： RON-MICHAEL BAR , ERAN GLICKMAN , AMIR DAVID MODAN
IPC分类号： G06F21/75
CPC分类号： G06F21/75 , G06F21/14 , G06F21/556 , G06F21/74
摘要： An apparatus including: circuitry configured to enable a delay of a process performed responsive to a detected processing event; and an configuration interface configured to enable pre-configuration by a user of at least one of one or more attributes of the delay, the process or the processing event.
摘要翻译：一种装置，包括：电路，被配置为能够响应于检测到的处理事件而执行处理的延迟; 以及配置接口，被配置为使得用户能够对延迟，处理或处理事件的一个或多个属性中的至少一个进行预配置。

3. 发明申请

US20140012655A1 SYSTEM AND METHOD FOR PURCHASING WITH A DISCOUNT IN EXCHANGE FOR SOCIAL MEDIA ADVERTISING 审中-公开
标题翻译：用于社会媒体广告交换的折扣购买系统和方法
公开(公告)号：US20140012655A1
公开(公告)日：2014-01-09
申请号：US13541776
申请日：2012-07-05
申请人： Ami POLAK , Gilad Waksman , Jonathan Shpigel , Michael Bar-Zeev
发明人： Ami POLAK , Gilad Waksman , Jonathan Shpigel , Michael Bar-Zeev
IPC分类号： G06Q30/02
CPC分类号： G06Q30/02 , G06Q50/01
摘要： A method of receiving discounts in exchange for social media advertising for items in a store, including, finding an item of interest at a store by a customer with a mobile device that is configured to execute a discount application; wherein an item code is displayed on or near the item; entering the item code into the mobile device; communicating the item code to a remote server computer to retrieve information about the item; retrieving the information about the item from the server, wherein the information includes one or more discount options that are provided responsive to publication of the item in a social network in which the customer participates; storing the information about the item and the discount options in a list that is accessible by the mobile device.
摘要翻译：一种接收折扣的方法，用于交换商店中的商品的社交媒体广告，包括由具有配置为执行折扣应用的移动设备的客户在商店处寻找感兴趣的商品; 其中项目代码显示在所述项目上或附近; 将项目代码输入移动设备; 将项目代码传送到远程服务器计算机以检索关于该项目的信息; 从所述服务器检索关于所述项目的信息，其中所述信息包括响应于所述项目在所述客户参与的社交网络中的发布而提供的一个或多个折扣选项; 将关于项目和折扣选项的信息存储在可由移动设备访问的列表中。

4. 发明申请

US20090185487A1 AUTOMATED ADVANCE LINK ACTIVATION 审中-公开
标题翻译：自动预警链接激活
公开(公告)号：US20090185487A1
公开(公告)日：2009-07-23
申请号：US12017432
申请日：2008-01-22
申请人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
IPC分类号： H04L1/00
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： Embodiments herein provide a transaction level mechanism that ensures that the links are operational right in time for the data flow, so that the data flow will not be impacted by delays associated with link recovery into the operational state. The path has links that have the ability to be in an inactive mode or an active mode. The embodiments herein transmit an “activation transmission” over the path to turn on the links within the path, before sending a data transfer (comprising packetized data) to turn on (wake up) the inactive links within the path, so that the actual data transfer does not experience any such start-up or wake-up delays.
摘要翻译：这里的实施例提供了一种事务级别机制，其确保链路在时间上对于数据流动是正确的操作，使得数据流不会受到与链路恢复到操作状态相关联的延迟的影响。路径具有能够处于非活动模式或活动模式的链接。这里的实施例在发送数据传输（包括分组化数据）之前在路径内打开路径上的链路来传送“激活传输”，以打开（唤醒）路径内的非活动链路，使得实际数据转移不会发生任何此类启动或唤醒延迟。

5. 发明授权

US07500062B2 Fast path memory read request processing in a multi-level memory architecture 有权
标题翻译：快速路径存储器在多级存储器架构中的读请求处理
公开(公告)号：US07500062B2
公开(公告)日：2009-03-03
申请号：US11282093
申请日：2005-11-17
申请人： Bruce Leroy Beukema , Michael Bar-Joshua , Alexander Mesh , Shaul Yifrach
发明人： Bruce Leroy Beukema , Michael Bar-Joshua , Alexander Mesh , Shaul Yifrach
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F9/3834 , G06F12/126
摘要： A circuit arrangement and method selectively reorder speculatively issued memory read requests being communicated to a lower memory level in a multi-level memory architecture. In particular, a memory read request that has been speculatively issued to a lower memory level prior to completion of a cache lookup operation initiated in a cache memory in a higher memory level may be reordered ahead of at least one previously received and pending request awaiting communication to the lower memory level. By doing so, the latency associated with the memory read request is reduced when the request results in a cache miss in the higher level memory, and as a result, system performance is improved.
摘要翻译：电路布置和方法选择性地重新排序在多级存储器体系结构中被推送的存储器读请求被传送到较低存储器级。特别地，在高级存储器级别的高速缓冲存储器中启动的高速缓存查找操作完成之前被推测地发布到较低存储器级别的存储器读取请求可以在至少一个先前接收到的等待通信的等待请求之前重新排序到较低的内存级别。通过这样做，当请求导致高级存储器中的高速缓存未命中时，与存储器读取请求相关联的延迟被减少，结果提高了系统性能。

6. 发明授权

US09661577B2 Power management module and method therefor 有权
公开(公告)号：US09661577B2
公开(公告)日：2017-05-23
申请号：US14505538
申请日：2014-10-03
申请人： Amir David Modan , Ron-Michael Bar , Eran Glickman
发明人： Amir David Modan , Ron-Michael Bar , Eran Glickman
IPC分类号： G08C17/00 , H04W52/02
CPC分类号： H04W52/0258 , H04W52/0235 , H04W52/028 , Y02D70/00
摘要： A power management module comprising a client monitoring component arranged to monitor idle periods for a client component, and derive at least one idle period characteristic value for the client component based at least partly on the monitoring of the idle periods therefore. The power management module further comprises a power mode control component arranged to receive an indication of the client component entering an idle state, cause the client component to be put into a reduced power mode upon expiry of a first period of time, and cause the client component to be brought out of the reduced power mode upon expiry of a second period of time. At least one of the first and second periods of time is configured based at least partly on the idle period characteristic value(s) derived by the client monitoring component for the client component.

7. 发明申请

US20150378730A1 SYSTEM ON A CHIP WITH MANAGING PROCESSOR AND METHOD THEREFOR 有权
标题翻译：具有管理处理器的芯片系统及其方法
公开(公告)号：US20150378730A1
公开(公告)日：2015-12-31
申请号：US14316876
申请日：2014-06-27
申请人： NIR ATZMON , RON-MICHAEL BAR , ERAN GLICKMAN , STAS YOSUPOV
发明人： NIR ATZMON , RON-MICHAEL BAR , ERAN GLICKMAN , STAS YOSUPOV
IPC分类号： G06F9/30 , G06F11/30
CPC分类号： G06F9/30145 , G06F11/3024 , G06F11/3055 , G06F11/3433 , G06F2201/86 , G06F2201/87
摘要： A system on a chip comprises a managing processor for controlling operations of the system on a chip. The managing processor comprises a core monitor control logic circuit operable to: receive at least one instruction; determine whether the instruction is an activation instruction; determine whether the managing processor is in or transitioning to an idle state; and transition the managing processor from a first mode of operation to a second mode of operation in response to the instruction being an activation instruction and the managing processor being in or transitioning to an idle state.
摘要翻译：芯片上的系统包括用于控制芯片上的系统的操作的管理处理器。管理处理器包括核心监视器控制逻辑电路，其可操作以：接收至少一个指令; 确定指令是否是激活指令; 确定管理处理器是处于或转换到空闲状态; 以及响应于作为激活指令的指令并且所述管理处理器处于或转换到空闲状态，将所述管理处理器从第一操作模式转换到第二操作模式。

8. 发明授权

US07747803B2 Device, system, and method of handling delayed transactions 有权
标题翻译：处理延迟交易的设备，系统和方法
公开(公告)号：US07747803B2
公开(公告)日：2010-06-29
申请号：US11946102
申请日：2007-11-28
申请人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
IPC分类号： G06F13/00 , G06F13/14 , G06F3/00
CPC分类号： G06F13/36
摘要： Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.
摘要翻译：处理延迟交易的设备，系统和方法。例如，在计算系统中处理延迟事务的装置包括：适于伪随机拒绝从主单元接收的请求的从单元。

9. 发明申请

US20090187870A1 PLACEMENT DRIVEN ROUTING 有权
标题翻译：放置驱动路由
公开(公告)号：US20090187870A1
公开(公告)日：2009-07-23
申请号：US12018422
申请日：2008-01-23
申请人： Shaul Yifrach , Michael Bar-Joshua , Itamar Tsachi , Boaz Yeger
发明人： Shaul Yifrach , Michael Bar-Joshua , Itamar Tsachi , Boaz Yeger
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method placing items routing wiring pursuant to integrated circuit specifications to create an integrated circuit design. Once the initially placed design is legalized, rather that just starting wiring routing, the method identifies books in the integrated circuit design which contain blocked items. The method allows the routing process to be paused temporarily, and for the items to be moved to a certain extent. This movement process is controlled (limited according to signal power output by the associated books) so that the timing of the integrated circuit design is not affected by any such “mid-routing” movement. If the books do not have any blocked items, the process continues to route wires between the items and the books. If at any point before or during the routing of the wires it is found that the books do have blocked items, the process pauses the routing of the wires and performs any number of different processes to solve the blocked item situation (unblock the blocked items).
摘要翻译：一种根据集成电路规范布置布线的方法来创建集成电路设计。一旦初始放置的设计合法化，而不仅仅是启动布线路由，该方法可以识别集成电路设计中包含阻塞项目的书籍。该方法允许临时暂停路由进程，并将项目移动到一定程度。该移动过程被控制（根据相关书籍的信号功率输出而限制），使得集成电路设计的时序不受任何这种“中间路由”移动的影响。如果这些书没有任何封闭的物品，该过程将继续在物品和书籍之间布线。如果在电线路由之前或期间的任何一点，发现这些书籍确实有阻塞的项目，该过程将暂停线路的路由并执行任意数量的不同进程来解决阻塞的项目情况（解除阻塞的项目）。

10. 发明申请

US20090138641A1 Device, System, and Method of Handling Delayed Transactions 有权
标题翻译：设备，系统和处理延迟交易的方法
公开(公告)号：US20090138641A1
公开(公告)日：2009-05-28
申请号：US11946102
申请日：2007-11-28
申请人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
IPC分类号： G06F13/18
CPC分类号： G06F13/36
摘要： Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.
摘要翻译：处理延迟交易的设备，系统和方法。例如，在计算系统中处理延迟事务的装置包括：适于伪随机拒绝从主单元接收的请求的从单元。

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