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1. 发明申请

US20080267281A1 METHOD, DEVICE AND NETWORK ELEMENT FOR DECODING AN INFORMATION WORD FROM A CODED WORD 审中-公开
标题翻译：用于从编码字解码信息字的方法，装置和网络单元
公开(公告)号：US20080267281A1
公开(公告)日：2008-10-30
申请号：US12107754
申请日：2008-04-22
申请人： Carlo COSTANTINI , Luigi Ronchetti , Silvio Cucchi
发明人： Carlo COSTANTINI , Luigi Ronchetti , Silvio Cucchi
IPC分类号： H04B1/66
CPC分类号： H03M13/09 , H04L1/0045 , H04L1/0057 , H04L1/007 , H04L1/0072 , H04L2001/0093
摘要： It is disclosed a method for decoding an information word from a set of coded words. The method comprises the steps of receiving a coded word, of selecting a coded word having the minimum distance from the received coded word from a pre-configured sub-set of the set of the coded words, wherein the sub-set is configured to at least two coded words having each other a distance higher than the minimum distance between the coded words of the set, and of decoding the information word from the selected coded word.
摘要翻译：公开了一种从一组编码字解码信息字的方法。该方法包括以下步骤：接收编码字，从编码字集合的预先配置的子集中选择具有来自接收到的编码字的最小距离的编码字，其中该子集被配置为至少两个编码字彼此具有比集合的编码字之间的最小距离高的距离，以及从所选择的编码字解码信息字。

2. 发明授权

US07126943B2 Method and apparatus for interfacing a parallel connection 失效
公开(公告)号：US07126943B2
公开(公告)日：2006-10-24
申请号：US10180126
申请日：2002-06-27
申请人： Silvio Cucchi , Luigi Ronchetti , Carlo Costantini
发明人： Silvio Cucchi , Luigi Ronchetti , Carlo Costantini
IPC分类号： H04Q11/02 , H04J1/00 , H04J3/04 , H04J14/00
CPC分类号： H04L1/0065 , H04J3/1611 , H04J3/1635 , H04L25/14 , Y10S370/907
摘要： A method and apparatus for interfacing a parallel connection, the parallel connection transmitting high bit-rate signals for a short distance. The method comprises: receiving a synchronous N-bits input data flow at a first input frequency; inserting said input data flow into parallel packets having a given length; and outputting said packets having a given length at a second output frequency onto a M-wires parallel connection. The method further comprises the steps of: defining an elementary packet comprising M lines and B+1 columns; defining a parallel packet by employing an integer number of said elementary packets, said number of elementary packets being chosen in order to maintain a constant phase relationship between the input frequency and the output frequency according to a number of parity lines in the elementary packet and to a code factor onto the parallel connection; inserting the input data flow into said parallel packet; and sending said parallel packet with the input data flow inserted therein into said parallel connection.

3. 发明授权

US5862410A System for controlling a variable source by the feedback of the running mode, and relevant circuit 失效
标题翻译：通过运行模式的反馈控制可变源的系统，以及相关电路
公开(公告)号：US5862410A
公开(公告)日：1999-01-19
申请号：US989728
申请日：1992-12-11
申请人： Luigi Ronchetti , Mario Stroppiana
发明人： Luigi Ronchetti , Mario Stroppiana
IPC分类号： G06F5/10 , G06F5/14 , H04N7/12 , H04N7/26
CPC分类号： G06F5/14 , G06F2205/061
摘要： A system for controlling the rate of flow of data generated by a variable rate data source and fed to a buffer which outputs the data at a constant bit rate. The operating mode, which sets the bit rate of the variable rate data source, is determined not only by the degree to which the buffer is filled, but also by the immediately preceding operating mode. The feedback of the operating mode results in an hysteresis effect on the mode, thus reducing the number of changes of the rate of data generation and thereby increasing the transmission quality of the data generated and output from the system.
摘要翻译：一种用于控制由可变速率数据源产生的数据流的速率并被馈送到以恒定比特率输出数据的缓冲器的系统。设定可变速率数据源的比特率的操作模式不仅由缓冲器填充的程度决定，而且由紧接着的前一操作模式确定。操作模式的反馈导致对模式的滞后效应，从而减少了数据生成速率的变化数量，从而增加了从系统产生和输出的数据的传输质量。

4. 发明授权

US5005076A DCT video signal compression device with intrafield/interfield switching and adjustable high frequency filter 失效
标题翻译：具有场内/场间切换和可调高频滤波器的DCT视频信号压缩装置
公开(公告)号：US5005076A
公开(公告)日：1991-04-02
申请号：US489486
申请日：1993-03-06
申请人： Mario Stroppina , Luigi Ronchetti
发明人： Mario Stroppina , Luigi Ronchetti
IPC分类号： H04N7/30 , G06T9/00 , H03M7/30 , H04N1/41 , H04N7/26 , H04N7/32 , H04N7/36 , H04N7/50
CPC分类号： H04N19/82 , H04N19/152 , H04N19/503 , H04N19/61 , H04N19/80 , H04N19/50
摘要： The digital signal is decomposed in intrafield blocks each comprising a set number of adjacent image elements, and each intrafield block, or an intrafield block or an interframe block derived therein, is subjected to a Discrete Cosine Transform and the transformed signal is applied to quantizer to generate a quantized signal which is encoded at variable length and loaded to a transmission buffer, the quantization resolution being inversely proportional to the buffer fill rate. According to the invention, a digital low-pass filter is connected to filter the block to be subjected to Discrete Cosine Transform, and is subjected to the buffer so that its upper-frequency cutoff lowers as the buffer fill rate increases.

5. 发明授权

US08429511B2 Equipment protection method and apparatus 有权
标题翻译：设备保护方法及装置
公开(公告)号：US08429511B2
公开(公告)日：2013-04-23
申请号：US12592140
申请日：2009-11-18
申请人： Silvio Cucchi , Giuseppe Badalucco , Carlo Costantini , Riccardo Gemelli , Luigi Ronchetti
发明人： Silvio Cucchi , Giuseppe Badalucco , Carlo Costantini , Riccardo Gemelli , Luigi Ronchetti
IPC分类号： G06F11/00
CPC分类号： H04Q3/68 , H04L49/101 , H04L49/552 , H04Q3/54558
摘要： Equipment protection of a switch matrix (SM) in a network node, which contains a number of matrix modules (M1.1-M4.4, E1.5-E4.6) is achieved by slicing an input signal into k parallel signal slices (x(0)-x(3)) with k>2; coding the k signal slices into a number of n coded signal slices (x(0)-x(5)) with n>k+1 using an error correcting code to add redundancy to said input signal; switching said n coded signal slices through the switching matrix (SM) via n distinct matrix modules; and decoding the n coded signal slices into k decoded signal slices to correct errors introduced while passing through said switch matrix. Preferably, the switch matrix (SM) contains a first number of matrix boards (MB1-MB4, EB5, EB6), each carrying a second number of matrix modules (M1.1-M4.4, E1.5-E4.6). The n coded signal slices are switched via matrix modules on n distinct matrix boards.
摘要翻译：通过将输入信号分割成k个并行信号片段来实现包含多个矩阵模块（M1.1-M4.4，E1.5-E4.6）的网络节点中的开关矩阵（SM）的设备保护（x（0）-x（3）），k> 2; 使用纠错码将k个信号片段编码为具有n> k + 1的n个编码信号片（x（0）-x（5））的数量，以向所述输入信号添加冗余; 通过开关矩阵（SM）通过n个不同的矩阵模块切换所述n个编码信号片; 以及将所述n个编码信号片段解码为k个解码信号片，以校正通过所述开关矩阵时引入的错误。优选地，开关矩阵（SM）包含第一数量的矩阵板（MB1-MB4，EB5，EB6），每个矩阵板承载第二数量的矩阵模块（M1.1-M4.4，E1.5-E4.6）。通过n个不同矩阵板上的矩阵模块切换n个编码信号片。

6. 发明申请

US20130028265A1 UPDATE OF A CUMULATIVE RESIDENCE TIME OF A PACKET IN A PACKET-SWITCHED COMMUNICATION NETWORK 有权
标题翻译：分组交换通信网络中的分组的累积驻留时间的更新
公开(公告)号：US20130028265A1
公开(公告)日：2013-01-31
申请号：US13637887
申请日：2011-04-14
申请人： Luigi Ronchetti , Riccardo Gemelli , Giorgio Cazzaniga , Carlo Costantini
发明人： Luigi Ronchetti , Riccardo Gemelli , Giorgio Cazzaniga , Carlo Costantini
IPC分类号： H04L12/56
CPC分类号： H04L43/106 , H04J3/0682 , H04J3/0697 , H04L43/0858
摘要： It is disclosed a method for updating a cumulative residence time of a synchronization packet received at a node of a packet-switched communication network. The cumulative residence time is equal to a cumulative sum of residence times of the packet at nodes interposed between a further node which has generated the packet and the node. The node comprises an ingress circuit and an egress circuit. The method comprises: receiving the packet at the egress circuit from the ingress circuit; at a timestamp generator of the egress circuit, generating a timestamp; at the egress circuit, calculating a virtual timestamp based on the timestamp and on an estimated variable delay that will be undergone by the packet due to buffering in a buffer located downstream the timestamp generator; and, at the egress circuit, using the virtual timestamp for updating the cumulative residence time, before transmitting the packet to a still further node.
摘要翻译：公开了一种用于更新在分组交换通信网络的节点处接收到的同步分组的累积停留时间的方法。累积停留时间等于插入在已经生成数据包的另一个节点和节点之间的节点处的数据包的驻留时间的累积和。节点包括入口电路和出口电路。该方法包括：从入口电路接收出口电路的分组; 在出口电路的时间戳发生器处产生时间戳; 在出口电路处，基于时间戳计算虚拟时间戳，以及由于位于时间戳发生器下游的缓冲器中缓冲而将由分组经历的估计可变延迟; 并且在出口电路处，在将分组发送到另一个节点之前，使用虚拟时间戳来更新累积停留时间。

7. 发明授权

US5072302A System for reducing the information transmitted in the variable length encoding of numerical data blocks with encoding of values and string lengths 失效
标题翻译：用于减少可变长度编码数字数据块中传输的信息的系统，编码值和长度
公开(公告)号：US5072302A
公开(公告)日：1991-12-10
申请号：US533522
申请日：1990-06-05
申请人： Luigi Ronchetti , Mario Stroppiana
发明人： Luigi Ronchetti , Mario Stroppiana
IPC分类号： H03M7/40 , G06T9/00 , H03M7/46
CPC分类号： G06T9/005 , H03M7/46
摘要： A method for reducing the information transmitted in the variable length encoding of numerical data blocks with encoding of single values and string lengths of a consecutive value ("run lengths"). Advantageously, the system eliminates that transmission of the last element in a string of recurrent values preceded by a "run length" and followed by another "run length" or by a data block end. When the string of recurrent values has a length of only one element, the single element is not transmitted.

8. 发明授权

US5006930A Device for reducing the redundancy in blocks of digital video data in DCT encoding 失效
标题翻译：用于减少DCT编码中的数字视频数据块的冗余的装置
公开(公告)号：US5006930A
公开(公告)日：1991-04-09
申请号：US489485
申请日：1990-03-06
申请人： Mario Stroppiana , Luigi Ronchetti
发明人： Mario Stroppiana , Luigi Ronchetti
IPC分类号： G06T9/00 , H03M1/00 , H03M7/30 , H04N1/41 , H04N7/30 , H04N7/50 , H04N11/04
CPC分类号： H04N19/18 , H04N19/126 , H04N19/152 , H04N19/60 , H04N19/61 , H04N19/146
摘要： A converter processes a digital video signal according to a known redundancy reducing algorithm executed on successive block for each frame or field and generates a transformed signal which is applied to a quantizer adapted to generate a quantized signal at preset transition levels on opposed sides of the zero, including the zero ( . . . ,-3,-2,-1, 0, 1, 2, 3, . . . ). The quantized signal is processed by a processor, adapted to determine the block length and the consecutive zero sequences along a preset scanning order, and to output a symbolic signal constituted by symbols indicating the quantization levels of the non-null data, the zero sequences and a symbol indicating the block end. The symbolic signal is applied to a variable length VLC encoder, adapted to encode data according to a preset designation law for generating a signal which is applied to a transmission buffer. The quantized signal generated by the quantizer further includes two ambiguous levels (x1 and x-1) at input values falling within respective preset intermediate ranges respectively between the zero level and the first positive level and between the zero level and the first negative level; the processor transforms each of the ambiguous levels respectively into a first positive level and a first negative level if the preceding and subsequent input values are both non-null and non-ambiguous, and transforms the ambiguous level into zero in all other cases.

9. 发明申请

US20130182716A1 DEVICE AND METHOD FOR SWITCHING DATA TRAFFIC IN A DIGITAL TRANSMISSION NETWORK 有权
标题翻译：用于在数字传输网络中切换数据业务的设备和方法
公开(公告)号：US20130182716A1
公开(公告)日：2013-07-18
申请号：US13819027
申请日：2011-09-28
申请人： Riccardo Gemelli , Luigi Ronchetti , Andrea Pararella , Vincenzo Sestito
发明人： Riccardo Gemelli , Luigi Ronchetti , Andrea Pararella , Vincenzo Sestito
IPC分类号： H04L12/56
CPC分类号： H04L49/30 , H04L49/1523 , H04L49/3072 , H04L49/606
摘要： A network element for a digital transmission network is proposed. The network element contains two switching matrices for switching data cells, as well as ingress ports that receive TDM traffic flow and packet traffic flow and segment the traffic flows into cells. A control system for controlling the configuration of the ingress ports and the switching matrices controls the ingress ports, in case of no failure of the switching matrices, to forward the TDM traffic flows to both switching matrices and to split the packet traffic flow over the two switching matrices.
摘要翻译：提出了一种用于数字传输网络的网元。网元包含两个用于切换数据单元的交换矩阵，以及接收TDM业务流和分组业务流的入口端口，并将业务流分段成小区。用于控制入口端口和交换矩阵的配置的控制系统控制入口端口，在交换矩阵不发生故障的情况下，将TDM业务流转发到两个交换矩阵，并将数据包业务流分为两个开关矩阵。

10. 发明授权

US09203725B2 Update of a cumulative residence time of a packet in a packet-switched communication network 有权
标题翻译：在分组交换通信网络中更新分组的累积停留时间
公开(公告)号：US09203725B2
公开(公告)日：2015-12-01
申请号：US13637887
申请日：2011-04-14
申请人： Luigi Ronchetti , Riccardo Gemelli , Giorgio Cazzaniga , Carlo Costantini
发明人： Luigi Ronchetti , Riccardo Gemelli , Giorgio Cazzaniga , Carlo Costantini
IPC分类号： H04L12/50 , H04L12/26 , H04J3/06
CPC分类号： H04L43/106 , H04J3/0682 , H04J3/0697 , H04L43/0858
摘要： It is disclosed a method for updating a cumulative residence time of a synchronization packet received at a node of a packet-switched communication network. The cumulative residence time is equal to a cumulative sum of residence times of the packet at nodes interposed between a further node which has generated the packet and the node. The node comprises an ingress circuit and an egress circuit. The method comprises: receiving the packet at the egress circuit from the ingress circuit; at a timestamp generator of the egress circuit, generating a timestamp; at the egress circuit, calculating a virtual timestamp based on the timestamp and on an estimated variable delay that will be undergone by the packet due to buffering in a buffer located downstream the timestamp generator; and, at the egress circuit, using the virtual timestamp for updating the cumulative residence time, before transmitting the packet to a still further node.
摘要翻译：公开了一种用于更新在分组交换通信网络的节点处接收到的同步分组的累积停留时间的方法。累积停留时间等于插入在已经生成数据包的另一个节点和节点之间的节点处的数据包的驻留时间的累积和。节点包括入口电路和出口电路。该方法包括：从入口电路接收出口电路的分组; 在出口电路的时间戳发生器处产生时间戳; 在出口电路处，基于时间戳计算虚拟时间戳，以及由于位于时间戳发生器下游的缓冲器中缓冲而将由分组经历的估计可变延迟; 并且在出口电路处，在将分组发送到另一个节点之前，使用虚拟时间戳来更新累积停留时间。

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