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1. 发明申请

US20100306627A1 RECEIVING APPARATUS, RECEIVING METHOD, PROGRAM, AND RECEIVING SYSTEM 有权
标题翻译：接收设备，接收方法，程序和接收系统
公开(公告)号：US20100306627A1
公开(公告)日：2010-12-02
申请号：US12783883
申请日：2010-05-20
申请人： Lui Sakai , Takashi Yokokawa
发明人： Lui Sakai , Takashi Yokokawa
IPC分类号： H03M13/07 , H03M13/05 , G06F11/10
CPC分类号： H03M13/116 , H03M13/09 , H03M13/1102 , H03M13/1185 , H03M13/15 , H03M13/152 , H03M13/2906 , H03M13/2945 , H03M13/356 , H03M13/616 , H03M13/6356 , H03M13/6362 , H03M13/6552 , H03M13/6555 , H04L1/0057 , H04L1/0065 , H04L1/0068 , H04L1/0071 , H04L27/2602
摘要： Disclosed herein is a receiving apparatus including a reception device configured to receive a code sequence coded in LDPC (Low Density Parity Check) and punctured at least partially as a target to be decoded; and an LDPC decoding device configured to perform a punctured matrix transform process including a first and a second process on an original parity check matrix noted to have punctured bits or symbols and used in the LDPC coding. The LDPC decoding device further performs the first process to carry out Galois field addition operations on those rows of the original parity check matrix to set the non-zero elements to zero. The LDPC decoding device further performs the second process to delete the columns rid of the non-zero elements. The LDPC decoding device uses the matrix resulting from the process as the parity check matrix for performing an LDPC decoding process on the code sequence.
摘要翻译：这里公开了一种接收装置，包括：接收装置，被配置为接收以LDPC（低密度奇偶校验）编码的码序列，并至少部分地作为要解码的目标进行穿孔; 以及LDPC解码装置，被配置为执行包括第一和第二处理的穿孔矩阵变换处理，所述原始奇偶校验矩阵被标记为具有穿孔比特或符号并用于LDPC编码。 LDPC解码装置还执行对原始奇偶校验矩阵的那些行执行伽罗瓦域加法运算的第一处理，以将非零元素设置为零。 LDPC解码装置还执行第二处理以删除非零元素的列。 LDPC解码装置使用由该处理得到的矩阵作为用于对码序列进行LDPC解码处理的奇偶校验矩阵。

2. 发明申请

US20100275101A1 DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：US20100275101A1
公开(公告)日：2010-10-28
申请号：US12744400
申请日：2008-11-26
申请人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
发明人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1165 , H03M13/036 , H03M13/255 , H03M13/2703 , H03M13/271 , H03M13/6552 , H04L1/0057 , H04L1/0071 , H04L27/3416 , H04L27/3488
摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.
摘要翻译：数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。解复用器根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中取代mb比特，并将替换后的码比特设置为b符号的符号比特。根据分配规则，分别将代码比特和符号比特的组合作为码比特组和符号比特组分别设定为组合的任何编码比特组以及要分配码位组的码位的符号位的符号位组，以及代码位和符号位的位编号。

3. 发明授权

US08578237B2 Data processing apparatus and data processing method 有权
标题翻译：数据处理装置及数据处理方法
公开(公告)号：US08578237B2
公开(公告)日：2013-11-05
申请号：US12744400
申请日：2008-11-26
申请人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
发明人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
IPC分类号： H03M13/00
CPC分类号： H03M13/1165 , H03M13/036 , H03M13/255 , H03M13/2703 , H03M13/271 , H03M13/6552 , H04L1/0057 , H04L1/0071 , H04L27/3416 , H04L27/3488
摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.
摘要翻译：数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。解复用器根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中取代mb比特，并将替换后的码比特设置为b符号的符号比特。根据分配规则，分别将代码比特和符号比特的组合作为码比特组和符号比特组分别设定为组合的任何编码比特组以及要分配码位组的码位的符号位的符号位组，以及代码位和符号位的位编号。

4. 发明申请

US20130166992A1 DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：US20130166992A1
公开(公告)日：2013-06-27
申请号：US13820808
申请日：2011-09-09
申请人： Yuji Shinohara , Makiko Yamamoto , Lui Sakai
发明人： Yuji Shinohara , Makiko Yamamoto , Lui Sakai
IPC分类号： H03M13/13
CPC分类号： H03M13/13 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/6552
摘要： The present invention relates to a data processing device and a data processing method capable of improving the resistance to data error. In a case where an LDPC code having a code length of 4,320 bits is mapped into 16 signal points, when a code bit of 4×2 bits and the (#i+1)-th bit from the most significant bit of symbol bits of 4×2 bits of two consecutive symbols are bits b#i and y#i, a demultiplexer performs an interchange process in which b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y1, b3 is allocated to y6, b4 is allocated to y2, b5 is allocated to y5, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 1/2, and b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y5, b3 is allocated to y2, b4 is allocated to y1, b5 is allocated to y6, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 7/12, 2/3, and 3/4. The present invention, for example, can be applied to a transmission system transmitting an LDPC code and the like.
摘要翻译：本发明涉及能够提高数据误差阻力的数据处理装置和数据处理方法。在具有4,320比特的码长的LDPC码被映射到16个信号点的情况下，当4×2比特的码比特和来自符号比特的最高有效位的（＃i + 1）比特两个连续符号的4×2位是位b＃i和y＃i，解复用器执行其中b0被分配给y0的交换处理，b1被分配给y4，b2被分配给y1，b3被分配给y6，将b4分配给y2，将b5分配给y5，将b6分配给y3，将b7分配给y7，对于编码速率为1/2的LDPC码，将b0分配给y0，将b1分配给y4， b2分配给y5，b3分配给y2，b4分配给y1，b5分配给y6，b6分配给y3，b7分配给y7，对于编码率为7/12的LDPC码，2 / 3和3/4。本发明例如可以应用于传输LDPC码等的传输系统。

5. 发明申请

US20100070820A1 CODING APPARATUS, CODING METHOD, CODING AND DECODING APPARATUS, AND COMMUNICATION APPARATUS 审中-公开
标题翻译：编码装置，编码方法，编码和解码装置以及通信装置
公开(公告)号：US20100070820A1
公开(公告)日：2010-03-18
申请号：US12516810
申请日：2007-12-14
申请人： Lui Sakai , Wataru Matsumoto , Hideo Yoshida
发明人： Lui Sakai , Wataru Matsumoto , Hideo Yoshida
IPC分类号： H03M13/05
CPC分类号： H03M13/116 , H03M13/6362
摘要： When carrying out puncturing of some redundant bits in an LDPC code having a check matrix of QC structure and LDGM structure, a puncture rule for preventing redundant bits which are chained to one another from being punctured is set up, and some redundant bits out of an LDPC-coded signal are punctured out of the LDPC-coded signal according to the puncture rule. As a result, redundant bits which are chained to one another can be left.
摘要翻译：当在具有QC结构和LDGM结构的校验矩阵的LDPC码中执行一些冗余位的删截时，建立用于防止相互链接的冗余位被打孔的穿孔规则，并且从根据穿孔规则，从LDPC编码信号中删除LDPC编码信号。结果，可以留下彼此链接的冗余位。

6. 发明申请

US20090138785A1 COMMUNICATION DEVICE, DECODING DEVICE, INFORMATION TRANSMISSION METHOD, AND DECODING METHOD 审中-公开
标题翻译：通信设备，解码设备，信息传输方法和解码方法
公开(公告)号：US20090138785A1
公开(公告)日：2009-05-28
申请号：US12293355
申请日：2007-03-15
申请人： Lui Sakai , Wataru Matsumoto , Hideo Yoshida
发明人： Lui Sakai , Wataru Matsumoto , Hideo Yoshida
IPC分类号： H03M13/05 , G06F11/07
CPC分类号： H03M13/1185 , H03M13/1102 , H03M13/1111 , H03M13/1117 , H03M13/353 , H03M13/356 , H03M13/616 , H03M13/618 , H03M13/6356 , H03M13/6362 , H03M13/6393 , H03M13/6527 , H03M13/6544 , H04L1/0057 , H04L1/0068 , H04L1/0083 , H04L1/1819
摘要： A communication device that transmits and receives LDPC-encoded information by using MIMO technology. The communication device includes a transmission sorting unit that sorts LDPC-encoded bits constituting the LDPC-encoded information in a descending order of column degree of a check matrix used for generating the LDPC-encoded bits; and a signal transmitting unit that transmits the LDPC-encoded bits sorted by the transmission sorting unit by allocating the LDPC-encoded bits from a transmission line having a lower noise level in sorted order.
摘要翻译：一种使用MIMO技术发送和接收LDPC编码信息的通信装置。通信装置包括发送分类单元，按照用于生成LDPC编码比特的校验矩阵的列顺序对构成LDPC编码信息的LDPC编码比特进行排序; 以及信号发送单元，其通过按照排序顺序从具有较低噪声电平的传输线分配LDPC编码比特来发送由发送分类单元排序的LDPC编码比特。

7. 发明授权

US08887030B2 Encoder and encoding method providing incremental redundancy 有权
标题翻译：编码和编码方法提供增量冗余
公开(公告)号：US08887030B2
公开(公告)日：2014-11-11
申请号：US13579735
申请日：2011-02-18
申请人： Nabil Loghin , Lothar Stadelmeier , Joerg Robert , Samuel Asangbeng Atungsiri , Makiko Yamamoto , Yuji Shinohara , Lui Sakai , Takashi Yokokawa
发明人： Nabil Loghin , Lothar Stadelmeier , Joerg Robert , Samuel Asangbeng Atungsiri , Makiko Yamamoto , Yuji Shinohara , Lui Sakai , Takashi Yokokawa
IPC分类号： H03M13/00 , H04L1/00 , H03M13/37 , H03M13/11
CPC分类号： H03M13/11 , H03M13/1165 , H03M13/3761 , H03M13/6519 , H04L1/0036 , H04L1/0045 , H04L1/0057 , H04L1/0059 , H04L1/0068 , H04L1/0083 , H04L2001/0098
摘要： The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number Kldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number Nldpc−Kldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number MIR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword portion (A) from an input data word (D) according to a second code, wherein an auxiliary parity symbol is generated by accumulating an information symbol m at a parity symbol address γ, wherein said parity symbol addresses γ are determined according to a second address generation rule Nldpc−Kldpc+{x+m mod Ga×QIR} mod MIR if x>Nldpc−Kldpc, wherein x denotes the addresses of a parity symbol accumulator corresponding to the first information symbol of a group of size Ga and QIR is an auxiliary code rate dependent, predefined constant, and an encoder output (1454) for outputting said codewords (Z1, Z2).
摘要翻译：本发明涉及一种用于将输入数据字（D）编码成码字（Z1，Z2）的纠错码的编码器，包括：编码器输入端（1451），用于接收输入数据字（D），每个输入数据字包括第一数字信号Kldpc 符号，用于将输入数据字（D）编码为码字（Z1，Z2，Z3，Z4）的编码装置（1452），使得码字包括基本码字部分（B），其包括数据部分（D）和基本奇偶校验符号的第二编号Nldpc-Kldpc的基本奇偶校验部分（Pb）和包括辅助奇偶校验符号的第三数量MIR的辅助奇偶校验部分（Pa）的辅助码字部分（A），其中所述编码装置）适于i）用于根据第一代码从输入数据字（D）产生所述基本码字部分（B），其中通过在根据第一代码确定的奇偶校验符号地址处累积信息符号来生成基本奇偶校验符号地址生成规则，和ii）生成s 根据第二代码从输入数据字（D）辅助辅助码字部分（A），其中通过在奇偶校验符号地址γ处累积信息符号m来生成辅助奇偶校验符号，其中所述奇偶校验符号地址γ根据如果x> Nldpc-Kldpc，则到第二地址生成规则Nldpc-Kldpc + {x + m mod Ga×QIR} mod MIR，其中x表示对应于大小为Ga的组的第一信息符号的奇偶校验符号累加器的地址， QIR是辅助代码速率相关的预定义常数，以及用于输出所述码字（Z1，Z2）的编码器输出（1454）。

8. 发明授权

US08448049B2 Receiving apparatus, receiving method, program, and receiving system 有权
标题翻译：接收装置，接收方法，程序和接收系统
公开(公告)号：US08448049B2
公开(公告)日：2013-05-21
申请号：US12783883
申请日：2010-05-20
申请人： Lui Sakai , Takashi Yokokawa
发明人： Lui Sakai , Takashi Yokokawa
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/09 , H03M13/1102 , H03M13/1185 , H03M13/15 , H03M13/152 , H03M13/2906 , H03M13/2945 , H03M13/356 , H03M13/616 , H03M13/6356 , H03M13/6362 , H03M13/6552 , H03M13/6555 , H04L1/0057 , H04L1/0065 , H04L1/0068 , H04L1/0071 , H04L27/2602
摘要： Disclosed herein is a receiving apparatus including a reception device configured to receive a code sequence coded in LDPC (Low Density Parity Check) and punctured at least partially as a target to be decoded; and an LDPC decoding device configured to perform a punctured matrix transform process including a first and a second process on an original parity check matrix noted to have punctured bits or symbols and used in the LDPC coding. The LDPC decoding device further performs the first process to carry out Galois field addition operations on those rows of the original parity check matrix to set the non-zero elements to zero. The LDPC decoding device further performs the second process to delete the columns rid of the non-zero elements. The LDPC decoding device uses the matrix resulting from the process as the parity check matrix for performing an LDPC decoding process on the code sequence.
摘要翻译：这里公开了一种接收装置，包括：接收装置，被配置为接收以LDPC（低密度奇偶校验）编码的码序列，并至少部分地作为要解码的目标进行穿孔; 以及LDPC解码装置，被配置为执行包括第一和第二处理的穿孔矩阵变换处理，所述原始奇偶校验矩阵被标记为具有穿孔比特或符号并用于LDPC编码。 LDPC解码装置还执行对原始奇偶校验矩阵的那些行执行伽罗瓦域加法运算的第一处理，以将非零元素设置为零。 LDPC解码装置还执行第二处理以删除非零元素的列。 LDPC解码装置使用由该处理得到的矩阵作为用于对码序列进行LDPC解码处理的奇偶校验矩阵。

9. 发明申请

US20120320994A1 ENCODER AND ENCODING METHOD PROVIDING INCREMENTAL REDUNDANCY 有权
标题翻译：编码和编码方法提供增值冗余
公开(公告)号：US20120320994A1
公开(公告)日：2012-12-20
申请号：US13579735
申请日：2011-02-18
申请人： Nabil Loghin , Lothar Stadelmeier , Joerg Robert , Samuel Asangbeng Atungsiri , Makiko Yamamoto , Yuji Shinohara , Lui Sakai , Takashi Yokokawa
发明人： Nabil Loghin , Lothar Stadelmeier , Joerg Robert , Samuel Asangbeng Atungsiri , Makiko Yamamoto , Yuji Shinohara , Lui Sakai , Takashi Yokokawa
IPC分类号： H04N7/56
CPC分类号： H03M13/11 , H03M13/1165 , H03M13/3761 , H03M13/6519 , H04L1/0036 , H04L1/0045 , H04L1/0057 , H04L1/0059 , H04L1/0068 , H04L1/0083 , H04L2001/0098
摘要： The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number Kldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number Nldpc−Kldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number MIR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword portion (A) from an input data word (D) according to a second code, wherein an auxiliary parity symbol is generated by accumulating an information symbol m at a parity symbol address γ, wherein said parity symbol addresses γ are determined according to a second address generation rule Nldpc−Kldpc+{x+m mod Ga×QIR} mod MIR if x>Nldpc−Kldpc, wherein x denotes the addresses of a parity symbol accumulator corresponding to the first information symbol of a group of size Ga and QIR is an auxiliary code rate dependent, predefined constant, and an encoder output (1454) for outputting said codewords (Z1, Z2).
摘要翻译：本发明涉及一种用于将输入数据字（D）编码成码字（Z1，Z2）的纠错码的编码器，包括：编码器输入端（1451），用于接收输入数据字（D），每个输入数据字包括第一数字信号Kldpc 符号，用于将输入数据字（D）编码为码字（Z1，Z2，Z3，Z4）的编码装置（1452），使得码字包括基本码字部分（B），其包括数据部分（D）和基本奇偶校验符号的第二编号Nldpc-Kldpc的基本奇偶校验部分（Pb）和包括辅助奇偶校验符号的第三数量MIR的辅助奇偶校验部分（Pa）的辅助码字部分（A），其中所述编码装置）适于i）用于根据第一代码从输入数据字（D）产生所述基本码字部分（B），其中通过在根据第一代码确定的奇偶校验符号地址处累积信息符号来生成基本奇偶校验符号地址生成规则，和ii）生成s 根据第二代码从输入数据字（D）辅助辅助码字部分（A），其中通过在奇偶校验符号地址γ处累积信息符号m来生成辅助奇偶校验符号，其中所述奇偶校验符号地址γ根据如果x> Nldpc-Kldpc，则到第二地址生成规则Nldpc-Kldpc + {x + m mod Ga×QIR} mod MIR，其中x表示对应于大小为Ga的组的第一信息符号的奇偶校验符号累加器的地址， QIR是辅助代码速率相关的预定义常数，以及用于输出所述码字（Z1，Z2）的编码器输出（1454）。

10. 发明申请

US20100281329A1 DATA PROCESSING APPARATUS, DATA PROCESSING METHOD AND PROGRAM 有权
标题翻译：数据处理设备，数据处理方法和程序
公开(公告)号：US20100281329A1
公开(公告)日：2010-11-04
申请号：US12743487
申请日：2008-11-26
申请人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
发明人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1165 , H03M13/1185 , H03M13/255 , H03M13/2703 , H03M13/2707 , H03M13/271 , H03M13/6552 , H03M13/6555 , H04L1/0057
摘要： The present invention relates to a data processing apparatus, a data processing method and a program which can improve the tolerance of code bits of an LDPC code to errors.Where two or more bits of an LDPC (Low Density Parity Check) code are set as one symbol and are mapped to 214 or 216 signal points, a column twist interleaver 24 carries out, as a re-arrangement process for re-arranging code bits of an LDPC code such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of a parity check matrix are not included in one symbol, column twist interleave of changing the writing starting position when code bits are written in a column direction of a memory for each column of the memory. The present invention can be applied, for example, to a transmission apparatus for transmitting an LDPC code.
摘要翻译：本发明涉及一种数据处理装置，数据处理方法和程序，其可以将LDPC码的码位的容限提高到错误。当LDPC（低密度奇偶校验）码的两个或多个比特被设置为一个符号并被映射到214或216个信号点时，列扭曲交织器24执行用于重新排列码位的重新排列处理使得与包括在奇偶校验矩阵的一个任意行中的值1相对应的多个码位不包括在一个符号中的LDPC码，当码位被写入列时改变写入起始位置的列扭曲交织存储器的每列的存储器方向。本发明可以应用于例如用于发送LDPC码的发送装置。

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