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1. 发明申请

US20080061835A1 Synchronizing modules in an integrated circuit 有权
标题翻译：在集成电路中同步模块
公开(公告)号：US20080061835A1
公开(公告)日：2008-03-13
申请号：US11900622
申请日：2007-09-11
申请人： Riccardo Locatelli , Marcello Coppola , Daniele Mangano , Luca Fanucci , Franscesco Vitullo , Dario Zandri , Nicola L'Insalata
发明人： Riccardo Locatelli , Marcello Coppola , Daniele Mangano , Luca Fanucci , Franscesco Vitullo , Dario Zandri , Nicola L'Insalata
IPC分类号： H03L7/00
CPC分类号： H04L7/0012 , H04L7/0045 , H04L7/02
摘要： A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK, RX_CLK) having a same frequency but being shifted by a constant and unknown phase difference. The system includes a first latch means for latching and delivering data in synchronism with the first clock signal and second latch means for latching data issued from the first latch means and delivering data in synchronism with the second clock signal, first and second latch means being controlled by first and second control signals (strobe_W, strobe_R) elaborated respectively from said first and second clock signals and one of said first and second control signal being shifted by an amount corresponding at least to the set-up time of at least one of said first and second latch means.
摘要翻译：一种同步系统，用于在诸如VLSI集成电路的集成电路中同步模块（TX，RX），其中模块接收具有相同频率但被偏移常数的相应的第一和第二时钟信号（TX_CLK，RX_CLK）未知相位差。该系统包括用于与第一时钟信号同步地锁存和传送数据的第一锁存装置和用于锁存从第一锁存装置发出的数据并与第二时钟信号同步传送数据的第二锁存装置，第一和第二锁存装置被控制通过分别从所述第一和第二时钟信号详细阐述的第一和第二控制信号（strobe_W，strobe_R），并且所述第一和第二控制信号中的一个被移位至少与所述第一和第二时钟信号中的至少一个的建立时间相对应的量和第二锁定装置。

2. 发明授权

US06466566B1 Low complexity adaptive interference mitigating CDMA detector 有权
标题翻译：低复杂度自适应干扰减轻CDMA检测器
公开(公告)号：US06466566B1
公开(公告)日：2002-10-15
申请号：US09247898
申请日：1999-02-10
申请人： Riccardo De Gaudenzi , Fillippo Giannetti , Javier Romero Garcia , Marco Luise , Luca Fanucci , Edoardo Letta
发明人： Riccardo De Gaudenzi , Fillippo Giannetti , Javier Romero Garcia , Marco Luise , Luca Fanucci , Edoardo Letta
IPC分类号： H04B7216
CPC分类号： H04J13/0044 , H04B1/71055 , H04B2201/70703 , H04J13/12
摘要： An adaptive signal receiver comprising at least one blind detection unit arranged to be robust to asynchronous multiple access interference (MAI). The useful signal is detected using a user signature sequence comprised of a fixed term and a complex adaptive part having a length that extends over a number of samples within a defined observation window. Provision is made for updating automatically and periodically the complex adaptive part of the signature sequence.
摘要翻译：一种自适应信号接收机，包括至少一个被布置为对异步多址干扰（MAI）是鲁棒的盲检测单元。使用由固定项和复数自适应部分组成的用户签名序列来检测有用的信号，所述复合自适应部分具有在限定的观察窗口内的多个样本上延伸的长度。提供了自动和周期性地更新签名序列的复杂自适应部分。

3. 发明授权

US08879670B2 Flexible channel decoder 有权
标题翻译：灵活的通道解码器
公开(公告)号：US08879670B2
公开(公告)日：2014-11-04
申请号：US12990721
申请日：2010-09-08
申请人： Giuseppe Gentile , Massimo Rovini , Paolo Burzigotti , Luca Fanucci
发明人： Giuseppe Gentile , Massimo Rovini , Paolo Burzigotti , Luca Fanucci
IPC分类号： H04L27/06
CPC分类号： H04L25/02 , H03M13/1111 , H03M13/1114 , H03M13/1117 , H03M13/1137 , H03M13/114 , H03M13/2957 , H03M13/2972 , H03M13/3905 , H03M13/3972 , H03M13/6508 , H03M13/6513 , H03M13/6519 , H03M13/6525 , H03M13/6527 , H03M13/653 , H03M13/6541 , H03M13/6544 , H03M13/6552 , H03M13/6555 , H03M13/6566 , H03M13/6569
摘要： A configurable Turbo-LDPC decoder having A set of P>1 Soft-Input-Soft-Output decoding units (DP0-DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of the decoding units having first (I1i) and second (I2i) input ports and first (O1i) and second (O2i) output ports for intermediate data; First and second memories (M1, M2) for storing the intermediate data, each of the first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of the decoding units to the output and input ports of the first memory, and the second input and output ports of the decoding units to the output and input ports of the second memory.
摘要翻译：一种可配置的Turbo-LDPC解码器，其具有用于迭代地解码Turbo和LDPC编码的输入数据的P> 1个软输入 - 软输出解码单元（DP0-DPP-1; DPi）集合，每个解码单元具有用于中间数据的第一（I1i）和第二（I2i）输入端口和第一（O1i）和第二（O2i）输出端口; 用于存储中间数据的第一和第二存储器（M1，M2），第一和第二存储器中的每一个包括具有相应输入和输出端口的P个独立可读和可写存储块; 和可配置交换网络（SN），用于将解码单元的第一输入和输出端口连接到第一存储器的输出和输入端口，以及将解码单元的第二输入和输出端口连接到第一存储器的输出和输入端口第二个记忆

4. 发明申请

US20090129390A1 Method for transferring a stream of at least one data packet between first and second electric devices and corresponding device 审中-公开
标题翻译：用于在第一和第二电气设备和对应设备之间传送至少一个数据分组的流的方法
公开(公告)号：US20090129390A1
公开(公告)日：2009-05-21
申请号：US12313364
申请日：2008-11-19
申请人： Giuseppe Maruccia , Riccardo Locatelli , Lorenzo Pieralisi , Marcello Coppola , Michele Casula , Luca Fanucci , Sergio Saponara
发明人： Giuseppe Maruccia , Riccardo Locatelli , Lorenzo Pieralisi , Marcello Coppola , Michele Casula , Luca Fanucci , Sergio Saponara
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/22 , H04L47/39 , H04L49/90 , H04L49/901
摘要： Systems and methods for transferring a stream of at least one data packet between a first electronic device and second electronic device through a network-on-chip are disclosed. These systems and methods can comprise storing data packets in memory means provided in a network interface and transferring data packets from the memory means to the second electronic device. Packets can be transferred from the memory means after a quantity of packets is stored in the memory means, the quantity of packets being determined according to a value of a control parameter.
摘要翻译：公开了通过片上网络在第一电子设备和第二电子设备之间传送至少一个数据分组流的系统和方法。这些系统和方法可以包括将数据分组存储在提供在网络接口中的存储器装置中，并将数据分组从存储装置传送到第二电子装置。在存储装置中存储数量的数据包之后，可以从存储装置传送数据包，根据控制参数的值确定数据包的数量。

5. 发明申请

US20090063931A1 Methods and architectures for layered decoding of LDPC codes with minimum latency 有权
标题翻译：用于以最小延迟对LDPC码进行分层解码的方法和体系结构
公开(公告)号：US20090063931A1
公开(公告)日：2009-03-05
申请号：US11897021
申请日：2007-08-27
申请人： Massimo Rovini , Francesco Rossi , Luca Fanucci
发明人： Massimo Rovini , Francesco Rossi , Luca Fanucci
IPC分类号： G06F11/10
CPC分类号： H03M13/1137 , H03M13/114
摘要： An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for a current layer are pipelined with acquisition of input data for a next layer, whereby the current layer and the next layer may attempt to use soft output information common to both layers. The serial processing unit is configured for delaying acquisition of input data for the next layer over a number of idle clock cycles. Latency due to the idle clock cycles is minimized by selectively modifying the sequence of layers through the decoding process and the sequence of messages processed by a certain layer.
摘要翻译：用于解码低密度奇偶校验编码输入数据的解码器的实施例包括以时钟周期工作的串行处理单元，以执行代码中的层的串行更新。用于产生当前层的输出数据的串行处理单元的操作通过获取下一层的输入数据进行流水线化，由此当前层和下一层可以尝试使用两层共同的软输出信息。串行处理单元被配置为在多个空闲时钟周期内延迟对下一层的输入数据的采集。通过选择性地通过解码过程和由某一层处理的消息序列来选择性地修改层序列，由于空闲时钟周期的延迟被最小化。

6. 发明授权

US07443908B2 Low complexity detection in digital receivers 有权
标题翻译：数字接收机中的低复杂度检测
公开(公告)号：US07443908B2
公开(公告)日：2008-10-28
申请号：US10300661
申请日：2002-11-19
申请人： Lorena Simoni , Andrea Concil , Giuseppe Avellone , Piero Castoldi , Hisashi Kobayashi , Luca Fanucci , Riccardo Grasso
发明人： Lorena Simoni , Andrea Concil , Giuseppe Avellone , Piero Castoldi , Hisashi Kobayashi , Luca Fanucci , Riccardo Grasso
IPC分类号： H04B1/00
CPC分类号： H04B1/7105 , H04B2201/70701 , H04J13/0044
摘要： A receiver for receiving digital signals exposed to intersymbol interference as well as multiple access interference the method including linearly detecting said signals by combating said intersymbol interference by equalizing said received digital signals as well as mitigating said multiple access interference by detecting said digital signals using sliding window detection.
摘要翻译：一种用于接收暴露于符号间干扰的数字信号以及多址干扰的接收机，该方法包括通过使所述接收到的数字信号相等来对抗所述码间干扰来线性检测所述信号，以及通过使用滑动窗口检测所述数字信号来减轻所述多址干扰检测。

7. 发明授权

US07359428B2 VDSL transmission employing multi-code multi carrier CDMA modulation 失效
标题翻译：采用多码多载波CDMA调制的VDSL传输
公开(公告)号：US07359428B2
公开(公告)日：2008-04-15
申请号：US10901976
申请日：2004-07-30
申请人： Massimo Rovini , Giovanni Vanini , Luca Fanucci
发明人： Massimo Rovini , Giovanni Vanini , Luca Fanucci
IPC分类号： H04B1/707
CPC分类号： H04L5/026 , H04B1/707
摘要： An improved transmission method for high-rate digital communication on unshielded twisted copper pairs for Very-High Speed Digital Subscriber Loop (VDSL) modems. The new modulation scheme is a Multi Code Multi Carrier Code Division Multiple Access, hereafter named MC2 CDMA. The system takes advantage from both the CDMA modulation and the Multi-Carrier transmission and, in addition, the channel throughput is increased adopting a multi-code approach. The novel scheme encompasses transmitter, channel and receiver loading.
摘要翻译：一种用于超高速数字用户环路（VDSL）调制解调器的非屏蔽双绞线对的高速数字通信的改进传输方法。新的调制方案是多码多载波码分多址，以下称为MC <2> CDMA。该系统利用CDMA调制和多载波传输两者，此外，采用多码方式增加了信道吞吐量。新颖的方案包括发射机，信道和接收机加载。

8. 发明授权

US5818868A Direct-sequence spread-spectrum receiver including code acquisition and detection using an autoadaptive threshold 失效
标题翻译：直接序列扩频接收机包括使用自适应阈值的码采集和检测
公开(公告)号：US5818868A
公开(公告)日：1998-10-06
申请号：US629852
申请日：1996-04-09
申请人： Riccardo De Gaudenzi , Luca Fanucci , Filippo Giannetti , Marco Luise
发明人： Riccardo De Gaudenzi , Luca Fanucci , Filippo Giannetti , Marco Luise
IPC分类号： H03H21/00 , H04B1/707 , H04J13/10
CPC分类号： H04B1/708 , H04B1/70755
摘要： The invention relates to the recognition of a spread spectrum data signal transmitted in code division multiple access communication systems. The invention provides a receiver whose code acquisition and detection circuit includes circuitry configured for detecting the signal received by using an audio adaptive detection threshold generated locally from the output signal of the detection circuit itself. The invention is used for example, in terrestrial or satellite radio communication systems.
摘要翻译：本发明涉及在码分多址通信系统中发送的扩频数据信号的识别。本发明提供了一种接收机，其代码采集和检测电路包括被配置用于通过使用从检测电路本身的输出信号本地产生的音频自适应检测阈值来检测所接收的信号的电路。本发明例如用于地面或卫星无线电通信系统中。

9. 发明授权

US08181083B2 Methods and architectures for layered decoding of LDPC codes with minimum latency 有权
标题翻译：用于以最小延迟对LDPC码进行分层解码的方法和体系结构
公开(公告)号：US08181083B2
公开(公告)日：2012-05-15
申请号：US11897021
申请日：2007-08-27
申请人： Massimo Rovini , Francesco Rossi , Luca Fanucci
发明人： Massimo Rovini , Francesco Rossi , Luca Fanucci
IPC分类号： G06F11/10
CPC分类号： H03M13/1137 , H03M13/114
摘要： An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for a current layer are pipelined with acquisition of input data for a next layer, whereby the current layer and the next layer may attempt to use soft output information common to both layers. The serial processing unit is configured for delaying acquisition of input data for the next layer over a number of idle clock cycles. Latency due to the idle clock cycles is minimized by selectively modifying the sequence of layers through the decoding process and the sequence of messages processed by a certain layer.
摘要翻译：用于解码低密度奇偶校验编码输入数据的解码器的实施例包括以时钟周期工作的串行处理单元，以执行代码中的层的串行更新。用于产生当前层的输出数据的串行处理单元的操作通过获取下一层的输入数据进行流水线化，由此当前层和下一层可以尝试使用两层共同的软输出信息。串行处理单元被配置为在多个空闲时钟周期内延迟对下一层的输入数据的采集。通过选择性地通过解码过程和由某一层处理的消息序列来选择性地修改层序列，由于空闲时钟周期的延迟被最小化。

10. 发明申请

US20050002441A1 VDSL transmission employing multi-code multi-carrier CDMA modulation 失效
标题翻译：采用多码多载波CDMA调制的VDSL传输
公开(公告)号：US20050002441A1
公开(公告)日：2005-01-06
申请号：US10901976
申请日：2004-07-30
申请人： Massimo Rovini , Giovanni Vanini , Luca Fanucci
发明人： Massimo Rovini , Giovanni Vanini , Luca Fanucci
IPC分类号： H04B1/707 , H04L5/02 , H04L23/02
CPC分类号： H04L5/026 , H04B1/707
摘要： An improved transmission method for high-rate digital communication on unshielded twisted copper pairs for Very-High Speed Digital Subscriber Loop (VDSL) modems. The new modulation scheme is a Multi Code Multi Carrier Code Division Multiple Access, hereafter named MC2 CDMA. The system takes advantage from both the CDMA modulation and the Multi-Carrier transmission and, in addition, the channel throughput is increased adopting a multi-code approach. The novel scheme encompasses transmitter, channel and receiver. loading.
摘要翻译：一种用于超高速数字用户环路（VDSL）调制解调器的非屏蔽双绞线对的高速数字通信的改进传输方法。新的调制方案是多码多载波码分多址，以下称为MC <2> CDMA。该系统利用CDMA调制和多载波传输两者，此外，采用多码方式增加了信道吞吐量。新颖的方案包括发射机，信道和接收机。加载。

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