专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06949948B2 Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges 有权
标题翻译：数字逻辑器件具有极度偏斜的跳变点和复位电路，用于快速传播信号边沿
公开(公告)号：US06949948B2
公开(公告)日：2005-09-27
申请号：US10336503
申请日：2003-01-03
申请人： John D. Porter , Dean D. Gans , Larren G. Weber
发明人： John D. Porter , Dean D. Gans , Larren G. Weber
IPC分类号： H03K19/017 , H03K19/0175
CPC分类号： H03K19/01721
摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.
摘要翻译：本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。此外，实际上所有的输入门加载都用于传播的快速边缘。此外，如本文所公开的复位网络由至少两个门缓冲，从而减少由倾斜逻辑器件的输入或输出所看到的负载。

2. 发明授权

US06310820B1 Relaxed write timing for a memory device 有权
标题翻译：轻松的记忆设备的写时序
公开(公告)号：US06310820B1
公开(公告)日：2001-10-30
申请号：US09335195
申请日：1999-06-17
申请人： John D. Porter , William N. Thompson , Larren G. Weber
发明人： John D. Porter , William N. Thompson , Larren G. Weber
IPC分类号： G11C800
CPC分类号： G11C7/22
摘要： A memory device provides a relaxed write timing scheme that improves access time. The address and/or the data is set up to the memory array during a previous write cycle so that the next write cycle can proceed without delays produced in delivering the address and/or the data to the array during the write cycle in which the data is to be written to the array.
摘要翻译：存储器件提供了一种改善访问时间的轻松的写时序方案。地址和/或数据在先前写入周期期间被设置到存储器阵列，使得下一个写入周期可以在写入周期期间在数据传送期间产生延迟而进行，其中数据将被写入阵列。

3. 发明授权

US06239618B1 Buffer with fast edge propagation 有权
标题翻译：具有快速边缘传播的缓冲区
公开(公告)号：US06239618B1
公开(公告)日：2001-05-29
申请号：US09520057
申请日：2000-03-07
申请人： John D. Porter , Larren G. Weber , William N. Thompson
发明人： John D. Porter , Larren G. Weber , William N. Thompson
IPC分类号： H03K190175
CPC分类号： H03K5/023 , H03K5/12 , H03K5/1252
摘要： A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.
摘要翻译：具有第一和第二输入端子和输出端子的缓冲器。缓冲器还包括具有输入端和输出端的快速边沿驱动器，输入端连接到缓冲器的第一输入端，输出端连接到缓冲器的输出端。提供具有输入端子和输出端子的屏蔽电路，输入端子连接到缓冲器的第二输入端子。该缓冲器还包括具有输入端和输出端的恢复电路，输入端连接到屏蔽电路的输出端，输出端连接到缓冲器的输出端。

4. 发明授权

US6026031A Relaxed write timing for a memory device 失效
标题翻译：轻松的记忆设备的写时序
公开(公告)号：US6026031A
公开(公告)日：2000-02-15
申请号：US78069
申请日：1998-05-13
申请人： John D. Porter , William N. Thompson , Larren G. Weber
发明人： John D. Porter , William N. Thompson , Larren G. Weber
IPC分类号： G11C7/22 , G11C16/04
CPC分类号： G11C7/22
摘要： A memory device provides a relaxed write timing scheme that improves access time. The address and/or the data is set up to the memory array during a previous write cycle so that the next write cycle can proceed without delays produced in delivering the address and/or the data to the array during the write cycle in which the data is to be written to the array.
摘要翻译：存储器件提供了一种改善访问时间的轻松的写时序方案。地址和/或数据在先前写入周期期间被设置到存储器阵列，使得下一个写入周期可以在写入周期期间在数据传送期间产生延迟而进行，其中数据将被写入阵列。

5. 发明授权

US5483175A Method for circuits connection for wafer level burning and testing of individual dies on semiconductor wafer 失效
标题翻译：半导体晶片上晶圆级燃烧和单个晶片测试电路连接方法
公开(公告)号：US5483175A
公开(公告)日：1996-01-09
申请号：US209665
申请日：1994-03-09
申请人： Aftab Ahmad , Larren G. Weber , Robert S. Green
发明人： Aftab Ahmad , Larren G. Weber , Robert S. Green
IPC分类号： G01R31/30 , G06F11/27 , G01R31/28 , H01L21/66
CPC分类号： G01R31/30 , G06F11/27
摘要： Integrated circuit devices on a wafer are tested by the use of test circuit on the integrated circuit devices which is connected by means of a grid. The grid is used to enable the test circuitry, and provides an ability to test the devices while still on the wafer. This facilitates burning in the wafer prior to singulating the parts, since it is not necessary to separately establish electrical connections at contact points on the individual integrated circuit devices. In one embodiment, an oscillator may be adjusted in speed so that further tests may be effected by changing a test speed through the test circuit. Response of the integrated circuits at different operating speeds is determined by the adjustment of the oscillator speed so that a timing signal used for the testing may be varied.
摘要翻译：通过在通过电网连接的集成电路器件上使用测试电路来测试晶片上的集成电路器件。电网用于启用测试电路，并提供在晶片上仍能测试器件的能力。这样在分割部件之前便有助于在晶片中燃烧，因为不需要在各个集成电路器件上的接触点处单独建立电连接。在一个实施例中，可以调节振荡器的速度，以便可以通过改变测试电路的测试速度来进行进一步的测试。通过调整振荡器速度来确定不同工作速度下的集成电路的响应，从而可以改变用于测试的定时信号。

6. 发明授权

US06628139B2 Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges 有权
标题翻译：数字逻辑器件具有极度偏斜的跳变点和复位电路，用于快速传播信号边沿
公开(公告)号：US06628139B2
公开(公告)日：2003-09-30
申请号：US09922027
申请日：2001-08-03
申请人： John D. Porter , Dean D. Gans , Larren G. Weber
发明人： John D. Porter , Dean D. Gans , Larren G. Weber
IPC分类号： H03K190175
CPC分类号： H03K19/01721
摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention included inverters, buffers, NOR gates, NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate a either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.
摘要翻译：本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。根据本发明的偏斜逻辑器件的实施例包括用于快速传播所选择的输入信号的“快速”边沿的反相器，缓冲器，或非门，NAND门。另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。此外，实际上所有的输入门加载都用于传播的快速边缘。此外，如本文所公开的复位网络由至少两个门缓冲，从而减少由倾斜逻辑器件的输入或输出所看到的负载。

7. 发明授权

US5424651A Fixture for burn-in testing of semiconductor wafers, and a semiconductor wafer 失效
标题翻译：用于半导体晶片的老化测试的夹具以及半导体晶片
公开(公告)号：US5424651A
公开(公告)日：1995-06-13
申请号：US858682
申请日：1992-03-27
申请人： Robert S. Green , Larren G. Weber
发明人： Robert S. Green , Larren G. Weber
IPC分类号： G01R15/12 , G01R31/26 , G01R31/00 , G01R31/28
CPC分类号： G01R31/2642
摘要： A semiconductor wafer testing fixture facilitates burn-in testing of multiple wafers, whereby individual wafers have an array of individual die or integrated circuit chips with their own test circuitry. The wafer has Vcc and Vss buses provided thereon which are coupled to the individual integrated circuit chips and test circuitry. The fixture has a housing sized to accommodate multiple semiconductor wafers in a selected orientation. The wafers are supported within the housing on corresponding shelves, which provides a back bias voltage to the wafer. The fixture has first and second conductive arms for supplying selected voltages to the Vcc and Vss buses for imparting test cycling of the integrated circuits. The first arm has multiple hands which engage the Vcc buses on the wafers supported on corresponding shelves. Likewise, the second arm has multiple second hands which engage the Vss buses on the wafers supported on corresponding shelves.
摘要翻译：半导体晶片测试夹具有助于多个晶片的老化测试，由此单个晶片具有各自的芯片阵列或具有其自身测试电路的集成电路芯片。晶片具有设置在其上的Vcc和Vss总线，其耦合到各个集成电路芯片和测试电路。夹具具有尺寸适于容纳多个选定取向的半导体晶片的壳体。晶片被支撑在壳体内的对应的搁架上，其向晶片提供反向偏置电压。固定装置具有用于向Vcc和Vss总线提供所选择的电压的第一和第二导电臂，用于赋予集成电路的测试循环。第一臂具有多个手，其在支撑在相应货架上的晶片上接合Vcc总线。类似地，第二臂具有多个秒针，其在支撑在相应的架上的晶片上接合Vss总线。

8. 发明授权

US07046038B2 Upward and downward pulse stretcher circuits and modules 失效
标题翻译：向上和向下的脉冲担架电路和模块
公开(公告)号：US07046038B2
公开(公告)日：2006-05-16
申请号：US10336386
申请日：2003-01-03
申请人： John D. Porter , Dean D. Gans , Larren G. Weber
发明人： John D. Porter , Dean D. Gans , Larren G. Weber
IPC分类号： H03K19/0175
CPC分类号： H03K19/01721
摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.
摘要翻译：本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。此外，实际上所有的输入门加载都用于传播的快速边缘。此外，如本文所公开的复位网络由至少两个门缓冲，从而减少由倾斜逻辑器件的输入或输出所看到的负载。

9. 发明授权

US06917222B2 Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges and systems including same 有权
标题翻译：具有极度偏移的跳变点和复位电路的数字逻辑器件用于快速传播信号边缘和包括其的系统
公开(公告)号：US06917222B2
公开(公告)日：2005-07-12
申请号：US10336527
申请日：2003-01-03
申请人： John D. Porter , Dean D. Gans , Larren G. Weber
发明人： John D. Porter , Dean D. Gans , Larren G. Weber
IPC分类号： H03K19/017 , H03K19/00
CPC分类号： H03K19/01721
摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.
摘要翻译：本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。此外，实际上所有的输入门加载都用于传播的快速边缘。另外，如本文公开的复位网络由至少两个门缓冲，从而减少由偏斜逻辑器件的输入或输出所看到的负载。

10. 发明授权

US06724218B2 Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges 有权
标题翻译：数字逻辑器件具有极度偏斜的跳变点和复位电路，用于快速传播信号边沿
公开(公告)号：US06724218B2
公开(公告)日：2004-04-20
申请号：US10336355
申请日：2003-01-03
申请人： John D. Porter , Dean D. Gans , Larren G. Weber
发明人： John D. Porter , Dean D. Gans , Larren G. Weber
IPC分类号： H03K190175
CPC分类号： H03K19/01721
摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.
摘要翻译：本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。此外，实际上所有的输入门加载都用于传播的快速边缘。此外，如本文所公开的复位网络由至少两个门缓冲，从而减少由倾斜逻辑器件的输入或输出所看到的负载。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式