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1. 发明授权

US08951857B2 Method for implanting ions in semiconductor device 有权
标题翻译：在半导体器件中注入离子的方法
公开(公告)号：US08951857B2
公开(公告)日：2015-02-10
申请号：US12913267
申请日：2010-10-27
申请人： Young-Sun Sohn , Seung-Woo Jin , Min-Yong Lee , Kyoung-Bong Rouh
发明人： Young-Sun Sohn , Seung-Woo Jin , Min-Yong Lee , Kyoung-Bong Rouh
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/265 , H01L21/26513 , H01L21/2658
摘要： The present invention provides various methods for implanting ions in a semiconductor device that substantially compensate for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate. Other methods for fabricating a semiconductor device improve distribution of transistor parameters across a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile, across the substrate.
摘要翻译：本发明提供了用于在半导体器件中注入离子的各种方法，其基本上补偿了在对衬底的整个表面进行均匀离子注入时产生的衬底的中心部分和边缘部分之间的阈值电压的差异。用于制造半导体器件的其它方法通过形成不均匀的沟道掺杂层或通过在衬底上形成不均匀的结分布来改善晶体管参数跨衬底的分布。

2. 发明授权

US08222101B2 Method of fabricating a MOS transistor having a gate insulation layer with a lateral portion and a vertical portion 有权
标题翻译：制造具有侧面部分和垂直部分的栅极绝缘层的MOS晶体管的方法
公开(公告)号：US08222101B2
公开(公告)日：2012-07-17
申请号：US11770168
申请日：2007-06-28
申请人： Kyoung-Bong Rouh
发明人： Kyoung-Bong Rouh
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/76 , H01L27/148 , H01L29/66 , H01L21/70 , H01L27/088 , H01L23/31 , H01L21/304
CPC分类号： H01L21/28167 , H01L29/42368 , H01L29/66659 , H01L29/78
摘要： A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer.
摘要翻译：抑制短沟道效应的MOS晶体管包括基板，第一扩散区域和第二扩散区域，所述基板，第一扩散区域和第二扩散区域通过基板的上部中的沟道区域彼此分离，栅极绝缘层，包括设置在基板上的第一栅极绝缘层沟道区域中的衬底的表面以及设置在第一扩散区域和沟道区域之间的具有从衬底的表面指定的深度的第二栅极绝缘层以及设置在第一栅极绝缘层上的栅电极。

3. 发明申请

US20100285642A1 Method of Doping Impurity Ions in Dual Gate and Method of Fabricating the Dual Gate using the same 审中-公开
标题翻译：双门掺杂杂质离子的方法及其制作方法
公开(公告)号：US20100285642A1
公开(公告)日：2010-11-11
申请号：US12558215
申请日：2009-09-11
申请人： Kyoung Bong Rouh , Yun Hyuck Ji , Tae Kyun Kim , Woo Sung Kim , Seung Mi Lee
发明人： Kyoung Bong Rouh , Yun Hyuck Ji , Tae Kyun Kim , Woo Sung Kim , Seung Mi Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of doping impurity ions in a dual gate includes doping first conductivity type impurity ions in a gate conductive layer over a semiconductor substrate having a first region and a second region, wherein the doping is performed with a concentration gradient so that a doping concentration in an upper portion of the gate conductive layer is higher than that in a lower portion; doping second conductivity type impurity ions in a portion of the gate conductive layer in the second region using a mask for opening the portion of the gate conductive layer in the second region; and diffusing the first conductivity type impurity ions and the second conductivity type impurity ions by performing heat treatment.
摘要翻译：在双栅极中掺杂杂质离子的方法包括在具有第一区域和第二区域的半导体衬底上的栅极导电层中掺杂第一导电型杂质离子，其中以浓度梯度进行掺杂，使得掺杂浓度栅极导电层的上部比下部高; 在第二区域中的栅极导电层的一部分中掺杂第二导电型杂质离子，使用掩模，用于在第二区域中打开栅极导电层的部分; 并通过进行热处理使第一导电型杂质离子和第二导电型杂质离子扩散。

4. 发明授权

US07790551B2 Method for fabricating a transistor having a recess gate structure 失效
标题翻译：一种制造具有凹槽栅结构的晶体管的方法
公开(公告)号：US07790551B2
公开(公告)日：2010-09-07
申请号：US12603906
申请日：2009-10-22
申请人： Kyoung Bong Rouh , Seung Woo Jin , Min Yong Lee , Yong Soo Jung
发明人： Kyoung Bong Rouh , Seung Woo Jin , Min Yong Lee , Yong Soo Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/4236 , H01L21/26586 , H01L21/28061 , H01L29/1041 , H01L29/516 , H01L29/66621
摘要： A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.
摘要翻译：具有凹陷栅极结构的晶体管及其制造方法。晶体管包括形成在形成在半导体衬底中的第一沟槽的内壁上的栅极绝缘层; 形成在所述栅极绝缘层上以部分地填充所述第一沟槽的栅极导电层; 栅极电极，形成在栅极导电层上，用于完全填充第一沟槽，并被栅极导电层包围; 形成在半导体衬底中的第一沟槽区; 以及形成在半导体衬底的浅部中的源极/漏极区域。

5. 发明授权

US07687350B2 Method for manufacturing semiconductor memory device using asymmetric junction ion implantation 失效
标题翻译：使用不对称结离子注入制造半导体存储器件的方法
公开(公告)号：US07687350B2
公开(公告)日：2010-03-30
申请号：US11450816
申请日：2006-06-09
申请人： Min Yong Lee , Kyoung Bong Rouh , Seung Woo Jin
发明人： Min Yong Lee , Kyoung Bong Rouh , Seung Woo Jin
IPC分类号： H01L21/336
CPC分类号： H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L29/1037 , H01L29/66621 , H01L29/66659
摘要： A method for manufacturing a semiconductor memory device using asymmetric junction ion implantation, including performing ion implantation for adjusting a threshold voltage to a semiconductor substrate, forming a gate stack on the semiconductor substrate to define a storage node junction region and a bit line junction region, implanting a first conductive impurity ion and a second conductive impurity ion using a mask layer pattern covering the storage node junction region while exposing the bit line junction region, forming a gate spacer layer at both sides of the gate stack, and implanting the first conductive impurity ion using the gate stack and the gate spacer layer as an ion implantation mask layer to form a storage node junction region and a bit line junction region having different impurity concentrations, and different junction depths from each other.
摘要翻译：一种制造使用非对称结离子注入的半导体存储器件的方法，包括执行用于调整对半导体衬底的阈值电压的离子注入，在半导体衬底上形成栅叠层以限定存储节点结区域和位线结区域，使用覆盖存储节点结区域的掩模层图案注入第一导电杂质离子和第二导电杂质离子，同时暴露位线结区域，在栅极堆叠的两侧形成栅极间隔层，以及注入第一导电杂质使用栅极堆叠和栅极间隔层作为离子注入掩模层，以形成具有不同杂质浓度和不同结深度的存储节点结区域和位线结区域。

6. 发明申请

US20080128640A1 Partial ion implantation apparatus and method using bundled beam 有权
标题翻译：部分离子注入装置和使用捆束的方法
公开(公告)号：US20080128640A1
公开(公告)日：2008-06-05
申请号：US11445643
申请日：2006-06-01
申请人： Kyoung Bong Rouh , Seung Woo Jin , Min Yong Lee , Yong Soo Jung
发明人： Kyoung Bong Rouh , Seung Woo Jin , Min Yong Lee , Yong Soo Jung
IPC分类号： H01J37/08
CPC分类号： H01J37/3172 , H01J37/045 , H01J2237/30472 , H01J2237/31703 , H01J2237/31708
摘要： An ion implantation apparatus comprises an ion beam source for generating an initial ion beam, a bundled ion beam generator adapted to change the initial ion beam into a bundled ion beam based on a predetermined frequency to pass the bundled ion beam for a first time while passing the initial ion beam for a second time, a beam line for accelerating the ion beam having passed through the ion beam generator, and an end station for arranging a wafer therein to allow the ion beam accelerated by the beam line to be implanted in the wafer, the end station operating to move the wafer in a direction perpendicular to an ion beam implantation direction, so as to implant the bundled ion beam in a first region of the wafer and the initial ion beam in a second region of the wafer.
摘要翻译：离子注入装置包括用于产生初始离子束的离子束源，捆扎离子束发生器，其适于基于预定频率将初始离子束改变成束状离子束，以在经过第一次时通过束状离子束初始离子束第二次，用于加速已经通过离子束发生器的离子束的束线，以及用于在其中布置晶片以使由束线加速的离子束被植入晶片的终端站，所述终端站操作以沿垂直于离子束注入方向的方向移动所述晶片，以将所述束状离子束注入所述晶片的第一区域中，并将所述初始离子束注入所述晶片的第二区域。

7. 发明授权

US07332772B2 Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same 有权
标题翻译：具有凹陷栅极和非对称掺杂剂区域的半导体器件及其制造方法
公开(公告)号：US07332772B2
公开(公告)日：2008-02-19
申请号：US11292381
申请日：2005-11-29
申请人： Kyoung Bong Rouh , Seung Woo Seung , Min Yong Lee
发明人： Kyoung Bong Rouh , Seung Woo Seung , Min Yong Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/7834 , H01L29/66621 , H01L29/66636
摘要： A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on the semiconductor such that the gate stack protrudes from the surface of the semiconductor substrate while the gate stack fills the trench, and first and second dopant regions disposed at the upper part of the semiconductor substrate adjacent to the first and second sidewalls of the trench, respectively, such that the first and second dopant regions have different steps.
摘要翻译：具有凹入栅极和不对称掺杂区域的半导体器件包括具有第一侧壁和第二侧壁的沟槽的半导体衬底，其高度彼此不同，设置在半导体衬底上的栅极绝缘层图案，设置在所述半导体上的栅极堆叠，使得所述栅极堆叠在所述栅极堆叠填充所述沟槽的同时从所述半导体衬底的表面突出;以及设置在所述半导体衬底的与所述第一和第二侧壁相邻的所述上部的第一和第二掺杂剂区域分别使得第一和第二掺杂剂区域具有不同的步骤。

8. 发明申请

US20050059226A1 Ion implantation method 有权
标题翻译：离子注入法
公开(公告)号：US20050059226A1
公开(公告)日：2005-03-17
申请号：US10880017
申请日：2004-06-29
申请人： Kyoung Bong Rouh , Seung Woo Jin , Bong Soo Kim
发明人： Kyoung Bong Rouh , Seung Woo Jin , Bong Soo Kim
IPC分类号： H01L21/265 , H01L21/425 , H01L21/44
CPC分类号： H01L21/26506 , H01L21/26513
摘要： Disclosed is an ion implantation method capable of preventing a channeling phenomenon caused by a lattice structure of a semiconductor substrate. The ion implantation method includes the steps of forming a predetermined mask pattern on the semiconductor substrate, performing an ion implantation process with respect to the semiconductor substrate exposed by the predetermined mask without forming a tilt angle, thereby forming an impurity area in the semiconductor substrate, and applying vibration to a lattice structure of the semiconductor substrate when the ion implantation process is carried out with respect to the semiconductor substrate.
摘要翻译：公开了一种能够防止由半导体衬底的晶格结构引起的沟道现象的离子注入方法。离子注入方法包括以下步骤：在半导体衬底上形成预定的掩模图案，对由预定掩模暴露的半导体衬底进行离子注入处理而不形成倾斜角，从而在半导体衬底中形成杂质区域，并且当相对于半导体衬底执行离子注入工艺时，对半导体衬底的晶格结构施加振动。

9. 发明授权

US08343859B2 Non-uniform ion implantation apparatus and method thereof 失效
标题翻译：非均匀离子注入装置及其方法
公开(公告)号：US08343859B2
公开(公告)日：2013-01-01
申请号：US12044722
申请日：2008-03-07
申请人： Kyoung Bong Rouh , Seung Woo Jin , Min Yong Lee
发明人： Kyoung Bong Rouh , Seung Woo Jin , Min Yong Lee
IPC分类号： H01L21/425
CPC分类号： H01J37/3171 , H01L21/265
摘要： A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predetermined direction while the wide ion beams generated by the wide ion beam generator are irradiated to the wafer. Among the wide ion beams, at least one wide ion beam has a different dose from that of at least one different wide ion beam. Since the wide ion beams are irradiated at different doses to the wafer, a smooth circular border is formed between the regions to which the impurity ions are implanted to different concentrations. Since the position of the wafer is suitably changed for the wide ion beams, it is possible to control disposition of the regions implanted with the impurity ions of different concentrations.
摘要翻译：不均匀离子注入装置包括宽离子束发生器，其被配置为产生多个宽离子束以照射晶片的整个区域上的至少两个区域，以及晶片旋转装置，其被配置为沿预定方向旋转晶片而由宽离子束发生器产生的宽离子束照射到晶片。在宽离子束中，至少一个宽离子束与至少一个不同的宽离子束的剂量不同。由于宽离子束以不同的剂量照射到晶片，所以在杂质离子被注入到不同浓度的区域之间形成平滑的圆形边界。由于对于宽离子束适当地改变晶片的位置，因此可以控制注入不同浓度的杂质离子的区域的配置。

10. 发明授权

US08110501B2 Method of fabricating landing plug with varied doping concentration in semiconductor device 失效
标题翻译：在半导体器件中制造具有不同掺杂浓度的着陆塞的方法
公开(公告)号：US08110501B2
公开(公告)日：2012-02-07
申请号：US12822461
申请日：2010-06-24
申请人： Kyoung Bong Rouh
发明人： Kyoung Bong Rouh
IPC分类号： H01L21/44
CPC分类号： H01L21/76895 , H01L21/28525 , H01L21/28556 , H01L27/10855 , Y10S438/923
摘要： A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug is divided into a first region, a second region, a third region, and a fourth region from a lower portion of the landing plug, and the first region is doped with a first doping concentration that is relatively lowest, the second region is doped with a second doping concentration that is higher than the first doping concentration, the third region is doped with a third doping concentration that is higher than the second doping concentration and the fourth region is not doped; and annealing the resulting product formed with the landing plug.
摘要翻译：一种在半导体存储器件中制造着陆塞的方法，其在一个实施例中包括在具有杂质区域的半导体衬底上形成着色插头接触孔以暴露杂质区; 通过用多晶硅层填充所述着陆塞接触孔来形成着陆塞，其中所述着陆塞从所述着陆塞的下部分为第一区，第二区，第三区和第四区，第一区域掺杂有相对较低的第一掺杂浓度，第二区域掺杂有高于第一掺杂浓度的第二掺杂浓度，第三区掺杂有高于第二掺杂浓度的第三掺杂浓度浓度和第四区域不掺杂; 并对由着陆塞形成的所得产品进行退火。

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