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1. 发明申请

US20120008726A1 DELAY LOCKED LOOP 有权
标题翻译：延迟锁定环
公开(公告)号：US20120008726A1
公开(公告)日：2012-01-12
申请号：US12880625
申请日：2010-09-13
申请人： Seon-Kwang JEON
发明人： Seon-Kwang JEON
IPC分类号： H03D3/24
CPC分类号： H03L7/0818
摘要： A delay locked loop includes a delay amount setting unit configured to set a delay amount of an external clock signal, a coarse delay unit configured to primarily delay the external clock signal by the set delay amount based on a first unit duration which is a unit delay amount of the coarse delay unit; and a fine delay unit configured to secondarily finely delay the primarily delayed clock signal based on a second unit duration, which is a unit delay amount of the fine delay unit and smaller than the first unit duration.
摘要翻译：延迟锁定环包括：延迟量设定单元，被配置为设置外部时钟信号的延迟量;粗略延迟单元，被配置为基于作为单位延迟的第一单位持续时间来主要将外部时钟信号延迟设定延迟量粗延迟单元的量; 以及精细延迟单元，其被配置为基于作为所述精细延迟单元的单位延迟量并小于所述第一单位持续时间的第二单位持续时间来二次精细地延迟所述主要延迟的时钟信号。

2. 发明授权

US07764100B2 DFLOP circuit for an externally asynchronous-internally clocked system 有权
标题翻译： DFLOP电路，用于外部异步内部时钟系统
公开(公告)号：US07764100B2
公开(公告)日：2010-07-27
申请号：US12171238
申请日：2008-07-10
申请人： Seon-Kwang Jeon
发明人： Seon-Kwang Jeon
IPC分类号： H03K3/00
CPC分类号： H03K3/356156
摘要： A DFLOP circuit for an EAIC system includes a resolver. The resolver includes a signal transmission controller that is activated under the control of an internal clock signal to receive and transmit an input signal, and a precharge unit that is activated in response to the internal clock signal to precharge an output node of the signal transmission controller.
摘要翻译：用于EAIC系统的DFLOP电路包括旋转变压器。解算器包括在内部时钟信号的控制下被激活以接收和发送输入信号的信号传输控制器，以及响应于内部时钟信号被激活以对信号传输控制器的输出节点进行预充电的预充电单元。

3. 发明授权

US07282702B2 Ion neutralizer 有权
标题翻译：离子中和器
公开(公告)号：US07282702B2
公开(公告)日：2007-10-16
申请号：US11174571
申请日：2005-07-06
申请人： Yun Kwang Jeon , Jung Wook Kim
发明人： Yun Kwang Jeon , Jung Wook Kim
IPC分类号： H05H3/02
CPC分类号： H05H3/02 , G21K1/14
摘要： An ion neutralizer enhances a heat transfer rate between a reflecting plate and a frame while preventing the reflecting plate from being bent due to thermal deformation. The ion neutralizer includes a frame and a plurality of reflecting plates integrally formed with the frame to neutralize plasma ions. Each reflecting plate has a cantilever shape. Each reflecting plate has a supporting end in surface contact with the frame, and a free end to define a space with the frame in order to prevent the reflecting plate from being bent upon stretching due to thermal deformation.
摘要翻译：离子中和器增强反射板和框架之间的传热速率，同时防止反射板由于热变形而弯曲。离子中和器包括框架和与框架整体形成以中和等离子体离子的多个反射板。每个反射板具有悬臂形状。每个反射板具有与框架表面接触的支撑端和与框架限定空间的自由端，以防止由于热变形而在拉伸时反射板弯曲。

4. 发明申请

US20060152164A1 Ion beam extractor 失效
标题翻译：离子束提取器
公开(公告)号：US20060152164A1
公开(公告)日：2006-07-13
申请号：US11208728
申请日：2005-08-23
申请人： Yung Hee Lee , Yun Kwang Jeon , Jin Seok Lee
发明人： Yung Hee Lee , Yun Kwang Jeon , Jin Seok Lee
IPC分类号： H01J1/46
CPC分类号： H01J37/08 , H01J27/024
摘要： An ion beam extractor controls a direction and an intensity of ion beams by adjusting a voltage applied to a grid having slits formed therein, thereby enhancing uniformity of an etching rate of a wafer, leading to an increase of productivity of semiconductor diodes. The ion beam extractor comprises an ion source to produce an ion beam and at least one grid located at a rear end of the ion source in a progressing path of the ion beam produced by the ion source to adjust a direction of the ion beam by controlling a voltage applied to the at least one grid.
摘要翻译：离子束提取器通过调节施加到其上形成有狭缝的栅格的电压来控制离子束的方向和强度，从而提高晶片的蚀刻速率的均匀性，从而提高半导体二极管的生产率。离子束提取器包括离子源以产生离子束和位于离子源的后端处的离子源的至少一个格栅，在由离子源产生的离子束的前进路径中，通过控制离子束来调节离子束的方向施加到所述至少一个栅格的电压。

5. 发明申请

US20090146129A1 MULTI-BIT MEMORY CELL STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：多位存储器单元结构及其制造方法
公开(公告)号：US20090146129A1
公开(公告)日：2009-06-11
申请号：US12330640
申请日：2008-12-09
申请人： Kwang-Jeon Kim
发明人： Kwang-Jeon Kim
IPC分类号： H01L45/00 , H01L21/441 , H01L23/485
CPC分类号： H01L45/1233 , H01L27/2463 , H01L45/06
摘要： A method of manufacturing a semiconductor memory cell including phase change material. A multi-bit memory cell may implement phase change material. Various kinds of information can be stored in one memory cell. A chip size may be minimized without sacrificing capacity and/or memory performance, as compared with a one-bit memory cell.
摘要翻译：一种制造包括相变材料的半导体存储单元的方法。多位存储单元可以实现相变材料。各种信息可以存储在一个存储单元中。与1位存储单元相比，芯片尺寸可以最小化，而不会牺牲容量和/或存储器性能。

6. 发明申请

US20090121745A1 DFLOP CIRCUIT FOR AN EXTERNALLY ASYNCHRONOUS-INTERNALLY CLOCKED SYSTEM 有权
标题翻译：用于外部异步内部时钟系统的DFLOP电路
公开(公告)号：US20090121745A1
公开(公告)日：2009-05-14
申请号：US12171238
申请日：2008-07-10
申请人： Seon Kwang Jeon
发明人： Seon Kwang Jeon
IPC分类号： H03K19/003
CPC分类号： H03K3/356156
摘要： A DFLOP circuit for an EAIC system includes a resolver. The resolver includes a signal transmission controller that is activated under the control of an internal clock signal to receive and transmit an input signal, and a precharge unit that is activated in response to the internal clock signal to precharge an output node of the signal transmission controller.
摘要翻译：用于EAIC系统的DFLOP电路包括旋转变压器。解算器包括在内部时钟信号的控制下被激活以接收和发送输入信号的信号传输控制器，以及响应于内部时钟信号被激活以对信号传输控制器的输出节点进行预充电的预充电单元。

7. 发明申请

US20080156771A1 ETCHING APPARATUS USING NEUTRAL BEAM AND METHOD THEREOF 审中-公开
标题翻译：使用中性光束的蚀刻装置及其方法
公开(公告)号：US20080156771A1
公开(公告)日：2008-07-03
申请号：US11965956
申请日：2007-12-28
申请人： Yun Kwang JEON , Jin Seok Lee , Yung Hee Lee , Gi Tae Kim
发明人： Yun Kwang JEON , Jin Seok Lee , Yung Hee Lee , Gi Tae Kim
IPC分类号： C23F1/00 , B44C1/22
CPC分类号： H01J37/3233 , H01J37/32357
摘要： An etching apparatus using a neutral beam includes an electron emission unit to convert an ion beam, extracted from plasma by a plurality of grids, into a neutral beam by colliding the ion beam with electrons to prevent the ion beam from physically colliding with the electron emission unit, thus preventing the damage to a neutralization unit and generation of foreign substances with a simple structure. Further, the etching apparatus converts the ion beam into the neutral beam at a high neutralizing efficiency without causing directionality and energy losses, and generates a neutral beam having a large area, thus uniformly etching a semiconductor wafer.
摘要翻译：使用中性光束的蚀刻装置包括电子发射单元，用于通过使离子束与电子碰撞来将通过多个栅极从等离子体提取的离子束转换成中性束，以防止离子束与电子发射物理碰撞单元，从而防止中和单元的损坏和结构简单的异物的产生。此外，蚀刻装置以高中和效率将离子束转换成中性光束，而不引起方向性和能量损失，并且产生具有大面积的中性光束，因此均匀地蚀刻半导体晶片。

8. 发明授权

US07285788B2 Ion beam extractor 失效
标题翻译：离子束提取器
公开(公告)号：US07285788B2
公开(公告)日：2007-10-23
申请号：US11208728
申请日：2005-08-23
申请人： Yung Hee Lee , Yun Kwang Jeon , Jin Seok Lee
发明人： Yung Hee Lee , Yun Kwang Jeon , Jin Seok Lee
IPC分类号： H01J27/00 , H01J49/42
CPC分类号： H01J37/08 , H01J27/024
摘要： An ion beam extractor controls a direction and an intensity of ion beams by adjusting a voltage applied to a grid having slits formed therein, thereby enhancing uniformity of an etching rate of a wafer, leading to an increase of productivity of semiconductor diodes. The ion beam extractor comprises an ion source to produce an ion beam and at least one grid located at a rear end of the ion source in a progressing path of the ion beam produced by the ion source to adjust a direction of the ion beam by controlling a voltage applied to the at least one grid.
摘要翻译：离子束提取器通过调节施加到其上形成有狭缝的栅格的电压来控制离子束的方向和强度，从而提高晶片的蚀刻速率的均匀性，从而提高半导体二极管的生产率。离子束提取器包括离子源以产生离子束和位于离子源的后端处的离子源的至少一个格栅，在由离子源产生的离子束的前进路径中，通过控制离子束来调节离子束的方向施加到所述至少一个栅格的电压。

9. 发明申请

US20070068624A1 APPARATUS TO TREAT A SUBSTRATE AND METHOD THEREOF 审中-公开
标题翻译：用于处理基板的方法及其方法
公开(公告)号：US20070068624A1
公开(公告)日：2007-03-29
申请号：US11532166
申请日：2006-09-15
申请人： Yun-kwang Jeon , Yung-hee Lee , Jin-seok Lee
发明人： Yun-kwang Jeon , Yung-hee Lee , Jin-seok Lee
IPC分类号： C23F1/00
CPC分类号： H01J37/321 , H01J37/32357
摘要： An apparatus to treat a substrate including a vacuum chamber having a plasma space where plasma is generated and a treating space where a substrate is treated, an extract electrode disposed between the plasma space and the treating space, a power supply to provide power to the extract electrode, and a controller to control the power supply so that a cation beam and a negative charge beam are alternately extracted from a plasma in the plasma space to the treating space.
摘要翻译：一种处理基板的设备，该基板包括具有产生等离子体的等离子体空间的真空室和处理基板的处理空间，设置在等离子体空间与处理空间之间的提取电极，向提取物提供电力的电源电极和控制器，以控制电源，使得阳离子束和负电荷束从等离子体空间中的等离子体交替提取到处理空间。

10. 发明授权

US08258838B2 Delay locked loop for expanding a delay range 有权
标题翻译：延迟锁定环，用于扩展延迟范围
公开(公告)号：US08258838B2
公开(公告)日：2012-09-04
申请号：US12880625
申请日：2010-09-13
申请人： Seon-Kwang Jeon
发明人： Seon-Kwang Jeon
IPC分类号： H03L7/06
CPC分类号： H03L7/0818
摘要： A delay locked loop includes a delay amount setting unit configured to set a delay amount of an external clock signal, a coarse delay unit configured to primarily delay the external clock signal by the set delay amount based on a first unit duration which is a unit delay amount of the coarse delay unit; and a fine delay unit configured to secondarily finely delay the primarily delayed clock signal based on a second unit duration, which is a unit delay amount of the fine delay unit and smaller than the first unit duration.
摘要翻译：延迟锁定环包括：延迟量设定单元，被配置为设置外部时钟信号的延迟量;粗略延迟单元，被配置为基于作为单位延迟的第一单位持续时间来主要将外部时钟信号延迟设定延迟量粗延迟单元的量; 以及精细延迟单元，其被配置为基于作为所述精细延迟单元的单位延迟量并小于所述第一单位持续时间的第二单位持续时间来二次精细地延迟所述主要延迟的时钟信号。

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