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1. 发明申请

US20120077312A1 FLIP-CHIP BONDING METHOD TO REDUCE VOIDS IN UNDERFILL MATERIAL 审中-公开
标题翻译：用于减少底层材料中挥发物的薄片粘结方法
公开(公告)号：US20120077312A1
公开(公告)日：2012-03-29
申请号：US13050538
申请日：2011-03-17
申请人： Kuo-Yuan LEE , Yung-Hsiang Chen , Wen-Chun Chiu , Kao-Hsiung Lin
发明人： Kuo-Yuan LEE , Yung-Hsiang Chen , Wen-Chun Chiu , Kao-Hsiung Lin
IPC分类号： H01L21/56
CPC分类号： H01L21/563 , H01L23/3121 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/75 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/06155 , H01L2224/06156 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/13562 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/32145 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/83102 , H01L2224/83192 , H01L2224/92125 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00013 , H01L2924/01029 , H01L2924/01079 , H01L2924/15787 , H01L2924/181 , H01L2924/351 , H01L2924/014 , H01L2924/00014 , H01L2924/01047 , H01L2924/01082 , H01L2224/13099 , H01L2924/00 , H01L2924/3512 , H01L2924/00012
摘要： Disclosed is a flip-chip bonding method to reduce voids in underfill material. A substrate with connecting pads is provided. At least a chip with a plurality of bumps is bonded on the substrate and then an underfill material is formed between the chip and the substrate. Finally, the substrate is placed in a pressure oven in which a positive pressure greater than one atm is provided, meanwhile, the underfill material is thermally cured with exerted pressures to reduce bubbles or voids trapped inside the underfill material to avoid popcorn issues due to CTE mismatch between the chip and the substrate. In one embodiment, another underfill material is further formed between a plurality of chips and bubbles or voids trapped between the chips are also reduced by the pressurized curing.
摘要翻译：公开了一种用于减少底部填充材料中的空隙的倒装焊接方法。提供具有连接焊盘的衬底。至少具有多个凸块的芯片接合在基板上，然后在芯片和基板之间形成底部填充材料。最后，将基板放置在其中提供大于一个大气压的正压力的压力烘箱中，同时，底部填充材料被施加的压力热固化以减少被困在底部填充材料内的气泡或空隙，以避免由于CTE引起的爆米花问题芯片和基板之间的不匹配。在一个实施例中，在多个芯片之间进一步形成另外的底部填充材料，并且还通过加压固化来减少捕获在芯片之间的气泡或空隙。

2. 发明申请

US20090294792A1 CARD TYPE MEMORY PACKAGE 审中-公开
标题翻译：卡类型存储包
公开(公告)号：US20090294792A1
公开(公告)日：2009-12-03
申请号：US12130518
申请日：2008-05-30
申请人： Kuo-Yuan Lee , Ke-Wen Lu , Ta-Wei Kuo , Wen-Chun Chiu , Pi-Wei Hsu
发明人： Kuo-Yuan Lee , Ke-Wen Lu , Ta-Wei Kuo , Wen-Chun Chiu , Pi-Wei Hsu
IPC分类号： H01L33/00
CPC分类号： G06K19/07745 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2225/0651 , H01L2924/00014 , H01L2924/01079 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/1815 , H01L2924/19105 , H01L2924/0002 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A card-type memory package is revealed, primarily comprising a substrate, a plurality of gold fingers, at least a memory chip, an LED chip, and an encapsulant. The memory chip and the LED chip are disposed on an encapsulated surface of the substrate with the LED chip adjacent to a rear side of the substrate. The gold fingers are attached to the substrate adjacent to a front side of the substrate. The encapsulant is formed on the encapsulated surface to encapsulate the memory chip and the LED chip with the gold fingers exposed. Therefore, the card-type memory package has the LED indication of reading and writing information with simplified assembling processes.
摘要翻译：显示了一种卡型存储器封装，主要包括基板，多个金指，至少存储芯片，LED芯片和密封剂。存储芯片和LED芯片设置在衬底的封装表面上，其中LED芯片与衬底的后侧相邻。金指与衬底的前侧相邻地附接到衬底。密封剂形成在封装的表面上，以封住存储芯片和带有金指的LED芯片。因此，卡式存储器包具有读取和写入信息的LED指示，具有简化的组装过程。

3. 发明申请

US20130266923A1 Interactive Multimedia Instructional System and Device 审中-公开
标题翻译：交互式多媒体教学系统与设备
公开(公告)号：US20130266923A1
公开(公告)日：2013-10-10
申请号：US13442872
申请日：2012-04-10
申请人： Kuo-Yuan Lee
发明人： Kuo-Yuan Lee
IPC分类号： G09B5/00
CPC分类号： G09B5/08
摘要： An interactive multimedia instructional system and device include a wireless guidance unit used by an instructor and plural wireless interaction units used by pupils. The wireless guidance unit and the wireless interaction units are connected wirelessly with a computer host loaded with a multisite and point-and-click operating system and instructional software. A display unit is connected with the computer host to display execution pictures of the instructional software and to display pointers by the wireless guidance unit and the wireless interaction units. The instructional software includes a group management program and a lesson plan editing interface on the display unit. As a result, one-to-many interactive multimedia teaching that is more enriched, vivid and effective can be achieved through this electronic instructional system, between the instructor and the pupils.
摘要翻译：交互式多媒体教学系统和装置包括由导师使用的无线引导单元和学生使用的多个无线互动单元。无线引导单元和无线交互单元与装载有多站点和点击操作系统和教学软件的计算机主机无线连接。显示单元与计算机主机连接以显示指导软件的执行画面，并通过无线引导单元和无线交互单元显示指针。教学软件在显示单元上包括组管理程序和课程计划编辑界面。因此，通过电子教学系统，教师和学生之间的一对多互动多媒体教学，可以更加丰富，生动有效地实现。

4. 发明申请

US20120264257A1 MOLD ARRAY PROCESS METHOD TO PREVENT EXPOSURE OF SUBSTRATE PERIPHERIES 审中-公开
标题翻译：模板周转过程防止曝光的方法
公开(公告)号：US20120264257A1
公开(公告)日：2012-10-18
申请号：US13086851
申请日：2011-04-14
申请人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
发明人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
IPC分类号： H01L21/56
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/565 , H01L23/13 , H01L23/49816 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/50 , H01L24/73 , H01L24/86 , H01L24/97 , H01L2224/0401 , H01L2224/04042 , H01L2224/06156 , H01L2224/1624 , H01L2224/2919 , H01L2224/32014 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4824 , H01L2224/50 , H01L2224/73203 , H01L2224/73215 , H01L2224/73219 , H01L2224/92147 , H01L2224/97 , H01L2924/00013 , H01L2924/01029 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/1515 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2224/85 , H01L2224/86 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： Disclosed is a mold array process (MAP) method to prevent exposure of peripheries of substrate units where the major characteristic is to implement two kinds of encapsulating materials in the MAP method in mass production. A first encapsulating material for encapsulating chips is formed on a substrate strip by molding to continuously encapsulate the substrate units and the scribe lines between adjacent substrate units. Prior to forming a second encapsulating material, a plurality of cut grooves are formed along the scribing lines by pre-cutting processes to penetrate through the substrate strip but without penetrating through the first encapsulating material and have such a width that a plurality of peripheries of the substrate units are exposed outside the scribing lines. Then, the second encapsulating material is filled into the cut grooves. Accordingly, the peripheries of the substrate units are still encapsulated with the remains of the second encapsulating material after singulation processes where the substrate units are singulated into individual semiconductor packages to prevent exposure of the peripheries of the substrate units.
摘要翻译：公开了一种模具阵列工艺（MAP）方法，用于防止在大规模生产中在MAP方法中实现两种封装材料的基板单元周围的暴露。用于封装芯片的第一封装材料通过模制而形成在衬底条上，以将衬底单元和划线连续封装在相邻衬底单元之间。在形成第二封装材料之前，通过预切割工艺沿着划刻线形成多个切割槽，以穿透衬底条而不穿透第一封装材料，并且具有这样的宽度：多个外围的衬底单元暴露在划线之外。然后，将第二封装材料填充到切割槽中。因此，衬底单元的周边仍然被第二封装材料的残余物封装在单独处理之后，其中衬底单元被分割成单独的半导体封装以防止衬底单元的周边暴露。

5. 发明申请

US20120187598A1 METHOD AND APPARATUS OF COMPRESSION MOLDING TO REDUCE VOIDS IN MOLDING COMPOUNDS OF SEMICONDUCTOR PACKAGES 审中-公开
标题翻译：用于减少半导体封装模制化合物中的电荷的压缩成型的方法和装置
公开(公告)号：US20120187598A1
公开(公告)日：2012-07-26
申请号：US13214459
申请日：2011-08-22
申请人： Kuo-Yuan LEE , Yung-Hsiang Chen
发明人： Kuo-Yuan LEE , Yung-Hsiang Chen
IPC分类号： B29C43/18
CPC分类号： H01L24/97 , B29C43/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/97 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/181 , H01L2924/00014 , H01L2224/85 , H01L2924/00
摘要： Disclosed are a method and an apparatus of compression molding to reduce voids in molding compounds of semiconductor packages. A compression mold jig set including a top mold and a bottom mold is provided and disposed inside a pressure chamber. A substrate disposed with chips is loaded on the top mold. An encapsulating material is filled in the cavity of the bottom mold. When heating the bottom mold to melt the encapsulating material, a positive air pressure more than 1 atm is provided in the pressure chamber in order to expel or reduce any bubbles trapped inside the encapsulating material. Then, the top mold is pressed downward to clamp with the bottom mold under the heating and high-pressure condition until the encapsulating material is pre-cured to transform a molding compound adhered to the substrate. Therefore, potential bubble trapped inside the molding compound can be eliminated or reduced to improve production yield, reliability and life time.
摘要翻译：公开了一种压缩成型方法和装置，以减少半导体封装的模塑料中的空隙。提供并设置包括顶模和底模的压缩模具夹具，并设置在压力室内。设置有芯片的基板被装载在顶模上。将封装材料填充到底模的空腔中。当加热底模以熔化封装材料时，在压力室中提供大于1atm的正空气压力，以便排出或减少封闭材料内的任何气泡。然后，在加热和高压条件下将顶模向下按压以与底模夹紧，直到封装材料预固化，以转化附着在基材上的模塑料。因此，可以消除或减少模塑料内部滞留的气泡，提高产量，可靠性和使用寿命。

6. 发明授权

US08112854B2 Tool holding device for a five-axis lathe 有权
标题翻译：五轴车床刀具保持装置
公开(公告)号：US08112854B2
公开(公告)日：2012-02-14
申请号：US12754173
申请日：2010-04-05
申请人： Kuo-Yuan Lee
发明人： Kuo-Yuan Lee
IPC分类号： B23B21/00 , B23B29/32
CPC分类号： B23B3/162 , B23Q1/017 , B23Q1/623 , Y10T29/5154 , Y10T82/2541 , Y10T82/2587 , Y10T82/2591
摘要： A tool holding device is disposed between a headstock unit and a tailstock unit of a five-axis lathe, and includes a saddle driven to move longitudinally, a cross-slide riding on the saddle and driven to move transversely, a turntable platform disposed on a base mount that is disposed on the cross-slide and driven to revolve about an upright axis, and a tool post mounted on a base rest that is disposed on the turntable platform and driven to move uprightly. An indexable turret is disposed on the tool post for holding tool bits such that the five-axis lathe can perform movements about five axes to machine a workpiece so as to obtain a complicated geometric shape, thereby reducing setup time and errors and increasing production.
摘要翻译：工具保持装置设置在五轴车床的主轴箱单元和尾座单元之间，并且包括被驱动以纵向移动的鞍座，骑在鞍座上的横向滑动并被驱动以横向移动;转台平台，其设置在基座安装件设置在十字滑块上并被驱动以围绕直立轴线旋转;以及工具柱，其安装在基座上，该工具柱设置在转盘平台上并被驱动以竖直移动。可转位转台设置在刀架上用于保持工具头，使得五轴车床可以执行大约五个轴的运动，以加工工件，从而获得复杂的几何形状，从而减少安装时间和错误并增加生产。

7. 发明授权

US08093104B1 Multi-chip stacking method to reduce voids between stacked chips 有权
标题翻译：多芯片堆叠方法，以减少堆叠芯片之间的空隙
公开(公告)号：US08093104B1
公开(公告)日：2012-01-10
申请号：US13042136
申请日：2011-03-07
申请人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
发明人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
IPC分类号： H01L21/00
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/565 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/85423 , H01L2224/85447 , H01L2224/8592 , H01L2224/97 , H01L2225/0651 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01059 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2224/92247 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2924/00014
摘要： A multi-chip stacking method to reduce voids between stacked chips is revealed. A first chip is disposed on a substrate, and a plurality of first bonding wires are formed by wire bonding to electrically connect the first chip and the substrate. A second chip is disposed on an active surface of the first chip where a dielectric layer and a FOW adhesive (film over wire) adhesive are attached onto a back surface of the second chip. The FOW adhesive partially encapsulates the first bonding wires and adheres to the active surface of the first chip. Then, the substrate is placed in a pressure oven to provide a positive pressure greater than one atm during thermally curing the FOW adhesive with exerted pressures. Accordingly, voids can be reduced inside the FOW adhesive during the multi-chip stacked processes where issues of poor adhesion and popcorn between chips can be avoided.
摘要翻译：揭示了减少堆叠芯片之间的空隙的多芯片堆叠方法。第一芯片设置在基板上，并且通过引线接合形成多个第一接合线以电连接第一芯片和基板。第二芯片设置在第一芯片的有源表面上，其中电介质层和FOW粘合剂（膜上电缆）粘合剂附着到第二芯片的背表面上。 FOW粘合剂部分地封装第一粘合线并粘附到第一芯片的有效表面。然后，在施加压力的FOW粘合剂热固化期间，将基底放置在压力烘箱中以提供大于1atm的正压。因此，在多芯片堆叠过程中，可以在FOW粘合剂内部减少空隙，其中可以避免芯片之间的粘附不良和爆米花的问题。

8. 发明申请

US20100219521A1 WINDOW TYPE SEMICONDUCTOR PACKAGE 审中-公开
标题翻译： WINDOW型半导体封装
公开(公告)号：US20100219521A1
公开(公告)日：2010-09-02
申请号：US12437837
申请日：2009-05-08
申请人： Kuo-Yuan LEE , Yung-Hsiang Chen , Wen-Chun Chiu
发明人： Kuo-Yuan LEE , Yung-Hsiang Chen , Wen-Chun Chiu
IPC分类号： H01L23/04
CPC分类号： H01L23/3128 , H01L21/563 , H01L21/565 , H01L23/13 , H01L23/3114 , H01L23/49816 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/50 , H01L24/86 , H01L2224/32014 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/4824 , H01L2224/48465 , H01L2224/73203 , H01L2224/73215 , H01L2224/83192 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A window-type semiconductor package is revealed, primarily comprising a substrate with an interconnection channel, a chip on the substrate, a die-attach adhesive between the chip and the substrate, and an encapsulant filling the interconnection channel. A first solder mask formed on the top surface of the substrate has a specific pattern. The die-attach adhesive bonds the active surface of the chip to the first solder mask with the bonding pads of the chip aligned inside the interconnection channel. The first solder mask has an opening to expose the interconnection channel and further to form an indentation from the interconnection channel to expose the top surface to prevent damaging of the active surface of the chip adjacent to the edges of the interconnection channel to ensure the integrity and yield of the final products.
摘要翻译：揭示了一种窗型半导体封装，主要包括具有互连通道的衬底，衬底上的芯片，芯片和衬底之间的芯片附着粘合剂以及填充互连通道的密封剂。形成在基板的顶表面上的第一焊料掩模具有特定的图案。芯片附着的粘合剂将芯片的有效表面与第一焊接掩模结合，芯片的焊盘在互连通道内对齐。第一焊接掩模具有用于暴露互连通道的开口，并且进一步从互连通道形成凹陷以露出顶表面，以防止相邻于互连通道的边缘的芯片的有效表面的损坏，以确保完整性和最终产品的产量。

9. 发明授权

US08815645B2 Multi-chip stacking method to reduce voids between stacked chips 有权
标题翻译：多芯片堆叠方法，以减少堆叠芯片之间的空隙
公开(公告)号：US08815645B2
公开(公告)日：2014-08-26
申请号：US13311257
申请日：2011-12-05
申请人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
发明人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
IPC分类号： H01L21/00 , H01L25/065 , H01L23/00 , H01L21/56 , H01L25/00 , H01L23/31
CPC分类号： H01L21/565 , H01L21/561 , H01L23/3128 , H01L24/04 , H01L24/06 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/05554 , H01L2224/06135 , H01L2224/06136 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/83191 , H01L2224/838 , H01L2224/85013 , H01L2224/85186 , H01L2224/8592 , H01L2224/85951 , H01L2224/97 , H01L2225/0651 , H01L2225/06565 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01059 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2224/92247 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： A multi-chip stacking method to reduce voids between stacked chips is revealed. A first chip is disposed on a substrate, and a plurality of first bonding wires are formed by wire bonding to electrically connect the first chip and the substrate. A second chip is disposed on an active surface of the first chip where a FOW (film over wire) adhesive is formed on a back surface of the second chip. The FOW adhesive partially encapsulates the first bonding wires and adheres to the active surface of the first chip. Then, the substrate is placed in a pressure oven to provide a positive pressure greater than one atm during thermally curing the FOW adhesive with exerted pressures. Accordingly, voids can be reduced inside the FOW adhesive during the multi-chip stacked processes where issues of poor adhesion and popcorn between chips can be avoided.
摘要翻译：揭示了减少堆叠芯片之间的空隙的多芯片堆叠方法。第一芯片设置在基板上，并且通过引线接合形成多个第一接合线以电连接第一芯片和基板。第二芯片设置在第一芯片的有源表面上，其中在第二芯片的背面上形成有FOW（覆膜上）粘合剂。 FOW粘合剂部分地封装第一粘合线并粘附到第一芯片的有效表面。然后，在施加压力的FOW粘合剂热固化期间，将基底放置在压力烘箱中以提供大于1atm的正压。因此，在多芯片堆叠过程中，可以在FOW粘合剂内部减少空隙，其中可以避免芯片之间的粘附不良和爆米花的问题。

10. 发明申请

US20120270368A1 MOLD ARRAY PROCESS METHOD TO ENCAPSULATE SUBSTRATE CUT EDGES 有权
标题翻译：用于封装底板切割边的模具阵列处理方法
公开(公告)号：US20120270368A1
公开(公告)日：2012-10-25
申请号：US13093476
申请日：2011-04-25
申请人： Kuo-Yuan LEE , Yung-Hsiang Chen , Wen-Chun Chiu
发明人： Kuo-Yuan LEE , Yung-Hsiang Chen , Wen-Chun Chiu
IPC分类号： H01L21/78
CPC分类号： H01L24/97 , H01L24/73 , H01L2224/32013 , H01L2224/32225 , H01L2224/48227 , H01L2224/4824 , H01L2224/50 , H01L2224/73215 , H01L2224/73265 , H01L2224/97 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/00012 , H01L2224/85 , H01L2924/00
摘要： Disclosed is a mold array process (MAP) method to encapsulate cut edges of substrate units. A substrate strip includes a plurality of substrate units arranged in a matrix. Scribe lines are defined between adjacent substrate units and at the peripheries of the matrix where pre-cut grooves are formed along the scribe lines with a width greater than the width of the scribe lines. An encapsulant is formed on the matrix of the substrate strip to continuously encapsulate the substrate units and the scribe lines to enable the encapsulant to fill into the pre-cut grooves to further encapsulate the cut edges of the substrate units. The cut edges of the substrate units are still encapsulated by the encapsulant even after singulation processes where substrate units are singulated into individual semiconductor packages to prevent the exposure of the plated traces of the substrate units to enhance the moisture resistance capability of the semiconductor packages.
摘要翻译：公开了一种用于封装基板单元的切割边缘的模具阵列工艺（MAP）方法。衬底条包括布置成矩阵的多个衬底单元。划线在相邻的基板单元之间以及在矩形的周边处被限定，其中沿着划线形成预切割槽，其宽度大于划线的宽度。在衬底条的矩阵上形成密封剂以连续地包封衬底单元和划痕线，以使密封剂能够填充到预切割凹槽中以进一步封装衬底单元的切割边缘。衬底单元的切割边缘即使在将衬底单元划分成单个半导体封装的单独处理之后仍然被密封剂封装，以防止衬底单元的电镀迹线的暴露，以增强半导体封装的耐湿性能。

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