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1. 发明申请

US20110167203A1 METHOD AND APPARATUS FOR CACHE CONTROL IN A DATA STORAGE DEVICE 审中-公开
公开(公告)号：US20110167203A1
公开(公告)日：2011-07-07
申请号：US13036662
申请日：2011-02-28
申请人： Kenji YOSHIDA , Tomonori MASUO , Shuichi ISHII , Kunio UTSUKI , Kazuya TAKADA
发明人： Kenji YOSHIDA , Tomonori MASUO , Shuichi ISHII , Kunio UTSUKI , Kazuya TAKADA
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0866 , G06F12/0804
摘要： According to one embodiment, a data storage device is provided, which has a cache controller that performs cache control, by using a buffer memory divided into segments, which are managed. The cache controller performs sequential hit judge on each segment, in accordance with the requested access range designated by a read or write command coming from a host system. The cache controller updates the hit upper-limit LBA set for each segment if the result of the hit judge is a mishit.

2. 发明申请

US20070094433A1 Access priority order setting apparatus and method 审中-公开
标题翻译：访问优先顺序设定装置及方法
公开(公告)号：US20070094433A1
公开(公告)日：2007-04-26
申请号：US11512094
申请日：2006-08-30
申请人： Kunio Utsuki , Kazuya Takada
发明人： Kunio Utsuki , Kazuya Takada
IPC分类号： G06F13/14
CPC分类号： G06F13/3625
摘要： An apparatus and method, which can certainly meet access requests and have flexibility, are disclosed. The apparatus includes a unit to be accessed, a slot sequence signal controller which has a plurality of slots, and associates identification information of an access request unit to an arbitrary slot, a request signal holding unit which holds request signals of the access request units, an access request recognition unit which recognizes sequentially and cyclically using identification information in the plurality of slots whether or not the request signal of the access request unit corresponding to the current identification information is held in the request signal holding unit, and an access permission unit which permits access of the corresponding access request unit when the request signal is confirmed.
摘要翻译：公开了一种能够满足访问请求并具有灵活性的装置和方法。该设备包括一个要访问的单元，一个具有多个时隙的时隙序列信号控制器，并将接入请求单元的识别信息与任意时隙相关联，一个请求信号保持单元，其保存访问请求单元的请求信号，访问请求识别单元，其在所述多个时隙中依次循环地识别与所述当前识别信息对应的所述访问请求单元的请求信号是否被保持在所述多个时隙中;以及访问许可单元，当请求信号被确认时允许对应的访问请求单元的访问。

3. 发明申请

US20110016264A1 METHOD AND APPARATUS FOR CACHE CONTROL IN A DATA STORAGE DEVICE 审中-公开
标题翻译：数据存储设备中缓存控制的方法和装置
公开(公告)号：US20110016264A1
公开(公告)日：2011-01-20
申请号：US12784334
申请日：2010-05-20
申请人： Kenji Yoshida , Tomonori Masuo , Shuichi Ishii , Kunio Utsuki , Kazuya Takada
发明人： Kenji Yoshida , Tomonori Masuo , Shuichi Ishii , Kunio Utsuki , Kazuya Takada
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08
CPC分类号： G06F12/0866 , G06F12/0804
摘要： According to one embodiment, a data storage device is provided, which has a cache controller that performs cache control, by using a buffer memory divided into segments, which are managed. The cache controller performs sequential hit judge on each segment, in accordance with the requested access range designated by a read or write command coming from a host system. The cache controller updates the hit upper-limit LBA set for each segment if the result of the hit judge is a mishit.
摘要翻译：根据一个实施例，提供了一种数据存储装置，其具有通过使用被分割成段的缓冲存储器来执行高速缓存控制的高速缓存控制器。高速缓存控制器根据来自主机系统的读取或写入命令指定的所请求的访问范围，对每个段执行顺序命中判断。如果命中判断的结果是mishit，则缓存控制器更新每个段的命中上限LBA集合。

4. 发明申请

US20100318842A1 CONTROLLER, STORAGE MEDIUM, AND INFORMATION CONTROL METHOD 审中-公开
标题翻译：控制器，存储介质和信息控制方法
公开(公告)号：US20100318842A1
公开(公告)日：2010-12-16
申请号：US12702178
申请日：2010-02-08
申请人： Kunio UTSUKI
发明人： Kunio UTSUKI
IPC分类号： G06F11/00 , G06F12/00 , G06F11/07
CPC分类号： G11B20/1803 , G11B20/10527 , G11B20/1833 , G11B2020/10629 , G11B2020/10657 , G11B2020/10796 , G11B2020/1843 , G11B2220/2516
摘要： According to one embodiment, a controller includes a receiver, an acquisition module, and a writer. The receiver receives information. The acquisition module acquires redundant information for correcting an error in the information. The writer writes the information to a first memory bank from a start address to a predetermined address of the first memory bank, and writes the redundant information to a second memory bank from the predetermined address to an end address of the second memory bank.
摘要翻译：根据一个实施例，控制器包括接收器，采集模块和写入器。接收器接收信息。采集模块获取用于纠正信息中的错误的冗余信息。写入器将信息从起始地址写入到第一存储体的预定地址，并将该冗余信息从预定地址写入第二存储体，到第二存储体的结束地址。

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