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1. 发明授权

US09912491B2 System and method for displaying document content using UPnP 有权
公开(公告)号：US09912491B2
公开(公告)日：2018-03-06
申请号：US12977466
申请日：2010-12-23
申请人： Ji-Hyeok Kim , Won-Sang Kwon , Tae-Hwan Hwang , Ki-Chul Park , Yoon-Suk Choi
发明人： Ji-Hyeok Kim , Won-Sang Kwon , Tae-Hwan Hwang , Ki-Chul Park , Yoon-Suk Choi
IPC分类号： G06F17/00 , H04L12/28 , G06F17/21 , H04L29/06
CPC分类号： H04L12/2812 , G06F17/21 , G06F17/211 , G06F17/212 , H04L12/2807 , H04L65/601
摘要： A system and method for displaying document content using Universal Plug and Play (UPnP) is provided. A media server provides meta information corresponding to the document content to a control point if a user request for displaying the document content is received, the control point provides the meta information of the document content to a media renderer that can display the requested document content together with an operation performance command for displaying the requested document content, and the media renderer receives the document content from the media server and renders the document content in accordance with the operation performance command to display the document content on a screen.

2. 发明申请

US20130220732A1 MUFFLER WITH DUAL EXHAUST GAS DISCHARGE PIPE FOR VEHICLE 有权
标题翻译：双排气排气管用于车辆
公开(公告)号：US20130220732A1
公开(公告)日：2013-08-29
申请号：US13619044
申请日：2012-09-14
申请人： Ki Chul PARK
发明人： Ki Chul PARK
IPC分类号： F01N1/10 , F01N1/24
CPC分类号： F01N1/083 , F01N1/084 , F01N1/10 , F01N2310/02 , F01N2340/00 , F01N2470/14 , F01N2470/18 , F01N2490/08
摘要： A muffler apparatus for a vehicle may include a muffler housing that has first and fourth chambers formed at front and rear portions therein and second and third chambers formed between the first and fourth chambers in sequence, an exhaust gas intake pipe that may be inserted in the muffler housing through the front portion of the muffler housing, with an end portion thereof being disposed in the third chamber, and exhaust gas discharge pipes that may be connected with the second chamber and discharge an exhaust gas to the outside of the muffler housing.
摘要翻译：用于车辆的消声器装置可以包括消音器壳体，其具有形成在其前部和后部的第一和第四腔室，以及依次形成在第一和第四腔室之间的第二和第三腔室，可以插入到第二腔室中的排气进气管消声器壳体，其消声器壳体的前部设置有第三室中的端部，以及排气排出管，其可以与第二室连接并将废气排放到消声器壳体的外部。

3. 发明授权

US08510396B2 Apparatus and method for storing content flip list of digital media server using user input feedback 有权
标题翻译：使用用户输入反馈来存储数字媒体服务器的内容翻转列表的装置和方法
公开(公告)号：US08510396B2
公开(公告)日：2013-08-13
申请号：US12859439
申请日：2010-08-19
申请人： Byung-Soo Lim , Ki-Chul Park , Sang-Won Ahn , Tae-Hwan Hwang , In-Young Shin , Joon-Oo Kim
发明人： Byung-Soo Lim , Ki-Chul Park , Sang-Won Ahn , Tae-Hwan Hwang , In-Young Shin , Joon-Oo Kim
IPC分类号： G06F15/16
CPC分类号： G06F17/30058 , G06F17/30035
摘要： Provided is a method for storing a content flip list of a digital media server using user input feedback. The method includes receiving a content request message from a user and transmitting the received request message to a media server, converting information received as a response to the request message into a page format, defining the converted information as a current page, and receiving and storing previous and next pages of the current page, and outputting the received current page through an output part.
摘要翻译：提供了一种使用用户输入反馈来存储数字媒体服务器的内容翻转列表的方法。该方法包括从用户接收内容请求消息，并将接收的请求消息发送到媒体服务器，将作为对请求消息的响应接收的信息转换为页面格式，将转换的信息定义为当前页面，以及接收和存储当前页面的上一页和下一页，并通过输出部分输出所接收的当前页面。

4. 发明申请

US20100140747A1 Semiconductor devices 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100140747A1
公开(公告)日：2010-06-10
申请号：US12592924
申请日：2009-12-04
申请人： Seung-Man Choi , Soon-Sik Hwang , Ki-Chul Park , Gi-Bum Kim , Ki-Su Kim , Sang-Chul Lee , Bae-Kyoung Kim
发明人： Seung-Man Choi , Soon-Sik Hwang , Ki-Chul Park , Gi-Bum Kim , Ki-Su Kim , Sang-Chul Lee , Bae-Kyoung Kim
IPC分类号： H01L23/58 , H01L23/522 , H01L21/768
CPC分类号： H01L23/585 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01322 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042
摘要： In a method of manufacturing a semiconductor device, a pad including at least one insulating interlayer and at least one conductive wiring may be formed in a pad area of a substrate. At least one wiring may be formed adjacent to the conductive wiring. At least one insulation layer may be formed adjacent to the insulating interlayer. At least one crack preventing structure may be formed in the insulation layer. The crack preventing structure may continuously extend in the insulation layer and portions of the insulation layer may also be continuous. When a semiconductor device includes at least one crack preventing structure disposed adjacent to a pad, a degradation of the semiconductor chip caused by an external impact and/or a stress may be efficiently prevented by the crack preventing structure.
摘要翻译：在制造半导体器件的方法中，可以在衬底的焊盘区域中形成包括至少一个绝缘中间层和至少一个导电布线的焊盘。可以在导电布线附近形成至少一个布线。可以在绝缘中间层附近形成至少一个绝缘层。至少一个防裂结构可以形成在绝缘层中。防裂结构可以在绝缘层中连续延伸，并且绝缘层的部分也可以是连续的。当半导体器件包括邻近焊盘设置的至少一个防裂结构时，可以通过防裂结构有效地防止由外部冲击和/或应力引起的半导体芯片的劣化。

5. 发明申请

US20100001186A1 METHOD OF MEASURING DIMENSION OF PATTERN AND RECORDING MEDIUM STORING PROGRAM FOR EXECUTING THE SAME 审中-公开
标题翻译：测量图案尺寸和记录中继储存程序的方法
公开(公告)号：US20100001186A1
公开(公告)日：2010-01-07
申请号：US12483997
申请日：2009-06-12
申请人： Soon-sik HWANG , Byung-sam Choi , Ki-chul Park
发明人： Soon-sik HWANG , Byung-sam Choi , Ki-chul Park
IPC分类号： G01N23/04
CPC分类号： H01J37/153 , H01J37/21 , H01J37/265 , H01J2237/1534 , H01J2237/216 , H01J2237/2826
摘要： A method of measuring a dimension of a measurement pattern by using a scanning electron microscope is provided. The method of measuring the dimension of the pattern includes: (a) moving to a correction pattern that is adjacent to the measurement pattern. The correction pattern comprises circular patterns to correct focus and/or stigmatism of the scanning electron microscope with respect to the correction pattern. The method further includes (b) measuring the dimension of the measurement pattern under measurement conditions to which the corrected focus and/or the stigmatism are reflected.
摘要翻译：提供了通过使用扫描电子显微镜测量测量图案的尺寸的方法。测量图案的尺寸的方法包括：（a）移动到与测量图案相邻的校正图案。校正图案包括用于校正扫描电子显微镜相对于校正图案的焦点和/或斑点的圆形图案。该方法还包括（b）在校正的焦点和/或标志被反映的测量条件下测量测量图案的尺寸。

6. 发明授权

US07365025B2 Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics 有权
标题翻译：使用具有不同孔隙率特性的多个平坦化层在半导体衬底上形成双镶嵌互连结构的方法
公开(公告)号：US07365025B2
公开(公告)日：2008-04-29
申请号：US11348428
申请日：2006-02-06
申请人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Oo Kim
发明人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Oo Kim
IPC分类号： H01L21/311
CPC分类号： H01L21/76808 , H01L21/31144
摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole.
摘要翻译：形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。

7. 发明授权

US07335590B2 Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby 有权
标题翻译：通过选择性地形成扩散阻挡层制造半导体器件的方法和由此制造半导体器件
公开(公告)号：US07335590B2
公开(公告)日：2008-02-26
申请号：US11033189
申请日：2005-01-11
申请人： Bong-Seok Suh , Ki-Chul Park , Seung-Man Choi , Il-Ryong Kim
发明人： Bong-Seok Suh , Ki-Chul Park , Seung-Man Choi , Il-Ryong Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/2855
摘要： In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substrate. The insulating layer is patterned, thereby forming an opening for exposing at least a portion of the conductive pattern. Then, a diffusion barrier layer is formed on the semiconductor substrate having the opening, using a selective deposition technique. The diffusion barrier layer is formed to a thickness that is less on the exposed conductive pattern than the thickness of the diffusion barrier layer on the insulating layer exposed inside the opening. Then, the diffusion barrier layer is etched, thereby forming a recessed diffusion barrier layer. In this manner, metal atoms are prevented from being diffused from a metal plug filling the opening or a metal interconnect to the insulating layer.
摘要翻译：在通过选择性地形成扩散阻挡层制造半导体器件的方法及其制造的半导体器件中，在半导体衬底上形成覆盖导电图案的导电图案和绝缘层。对绝缘层进行图案化，从而形成用于暴露导电图案的至少一部分的开口。然后，使用选择性沉积技术在具有开口的半导体衬底上形成扩散阻挡层。扩散阻挡层形成为暴露在导电图案上的厚度小于暴露在开口内部的绝缘层上的扩散阻挡层的厚度。然后，对扩散阻挡层进行蚀刻，从而形成凹陷扩散阻挡层。以这种方式，防止金属原子从填充开口的金属插塞或与绝缘层的金属互连扩散。

8. 发明申请

US20070155165A1 Methods for forming damascene wiring structures having line and plug conductors formed from different materials 有权
标题翻译：用于形成具有由不同材料形成的线和插头导体的镶嵌线结构的方法
公开(公告)号：US20070155165A1
公开(公告)日：2007-07-05
申请号：US11323328
申请日：2005-12-30
申请人： Ki-Chul Park , Ja-Hum Ku , Seung-Man Choi
发明人： Ki-Chul Park , Ja-Hum Ku , Seung-Man Choi
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76877 , H01L23/485 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure comprising a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.
摘要翻译：提供了用于形成使用不同导体材料填充通孔和线沟槽的双镶嵌互连结构的方法。例如，用于形成互连结构的方法包括在半导体衬底上沉积介电材料并蚀刻电介质材料以形成包括通孔和沟槽的双镶嵌凹部结构。然后共形沉积第一导电材料层以用第一导电材料填充通孔，并且蚀刻第一导电材料层以从沟槽移除第一导电材料，并且在沟槽下方的通孔的上部区域。然后沉积第二导电材料层，以用第二导电材料填充通孔的沟槽和上部区域。

9. 发明授权

US06884710B2 Semiconductor device having multi-layer copper line and method of forming same 有权
标题翻译：具有多层铜线的半导体器件及其形成方法
公开(公告)号：US06884710B2
公开(公告)日：2005-04-26
申请号：US10338908
申请日：2003-01-09
申请人： Ki-Chul Park , Seung-Man Choi
发明人： Ki-Chul Park , Seung-Man Choi
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76847 , H01L21/76868 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a lower copper line formed on a substrate, an interlayer insulating layer formed on the lower copper line, and an upper copper line formed on the interlayer insulating layer. A copper via contact extends through the interlayer insulating layer for electrically connecting the lower copper line and the upper copper line. A concave recess is formed within the lower copper line and is vertically aligned and arranged below the copper via contact. A patterned barrier layer is formed at a bottom portion of the concave recess, such that the lower copper line and the copper via contact are directly electrically connected at an interface along sides of the concave recess, without an intervening barrier layer.
摘要翻译：半导体器件包括形成在衬底上的下铜线，形成在下铜线上的层间绝缘层和形成在层间绝缘层上的上铜线。铜通孔接触件延伸穿过层间绝缘层，用于电连接下铜线和上铜线。在下铜线内部形成一个凹槽，并且垂直对齐并布置在铜通孔接触处的下方。图案化的阻挡层形成在凹形凹部的底部，使得下铜线和铜通路接触部在沿着凹形凹部的侧面的界面处直接电连接，而没有中间的阻挡层。

10. 发明授权

US06842028B2 Apparatus for testing reliability of interconnection in integrated circuit 有权
标题翻译：集成电路中互连可靠性的装置
公开(公告)号：US06842028B2
公开(公告)日：2005-01-11
申请号：US10766547
申请日：2004-01-27
申请人： Won-Sang Song , Jung-Woo Kim , Chang-Sub Lee , Sam-Young Kim , Young-Jin Wee , Ki-Chul Park
发明人： Won-Sang Song , Jung-Woo Kim , Chang-Sub Lee , Sam-Young Kim , Young-Jin Wee , Ki-Chul Park
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G01R31/2853
摘要： In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule. The unit part has vias formed through an interlayer dielectric layer at the both ends of a tooth parallel part, two tooth parallel parts connected with the vias, respectively, and a length parallel part electrically connecting two tooth parallel parts.
摘要翻译：在本发明中，一种测试集成电路互连的漏电保护可靠性的装置。该装置具有至少一个梳状图案，蛇形样图案和向图案施加偏压的装置，并且在形成在通孔周围的互连处形成最大场区域，即构成梳状图案在本发明的一个结构中，梳状图案形成在一个层面上，并且蛇形状图案分别具有对应于齿部的多个单位部分和连接相邻两个单元部分的连接部分。根据设计规则，每个单元部分与梳状图案形成在相同的高度上，并且与齿部分距离最小设计长度。单元部分具有通过在平行部分的两端处的层间绝缘层形成的通孔，分别与通孔连接的两个齿平行部分和电连接两个齿平行部分的长度平行部分。

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