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1. 发明授权

US09787612B2 Packet processing in a parallel processing environment 有权
公开(公告)号：US09787612B2
公开(公告)日：2017-10-10
申请号：US13487361
申请日：2012-06-04
申请人： Kenneth M. Steele , Vijay Aggarwal
发明人： Kenneth M. Steele , Vijay Aggarwal
IPC分类号： H04L12/861 , H04L12/869 , H04L12/873
CPC分类号： H04L49/90 , H04L47/52 , H04L47/60
摘要： Processing packets in a system that includes a plurality of interconnected processing cores is described. The processing includes receiving packets into one or more queues, associating at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate, mapping a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and at least one rate associated with a node not in the set, and processing the packets in the mapped processor cores according to the hierarchy.

2. 发明申请

US20130070588A1 Packet Processing in a Parallel Processing Environment 有权
标题翻译：并行处理环境中的数据包处理
公开(公告)号：US20130070588A1
公开(公告)日：2013-03-21
申请号：US13487361
申请日：2012-06-04
申请人： Kenneth M. Steele , Vijay Aggarwal
发明人： Kenneth M. Steele , Vijay Aggarwal
IPC分类号： H04L12/24 , H04L12/56
CPC分类号： H04L49/90 , H04L47/52 , H04L47/60
摘要： Processing packets in a system that comprises a plurality of interconnected processing cores includes: receiving packets into one or more queues; associating at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate; mapping a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and at least one rate associated with a node not in the set; and processing the packets in the mapped processor cores according to the hierarchy.
摘要翻译：在包括多个互连处理核心的系统中处理分组包括：将分组接收到一个或多个队列中; 将节点层级中的至少一些节点与至少一个队列相关联，并且至少一些节点与速率相关联; 基于集合中的节点的层级中的级别和与不在集合中的节点相关联的至少一个速率将一个或多个节点的集合映射到处理器核心; 并根据层次结构处理映射的处理器核心中的数据包。

3. 发明授权

US08620940B1 Pattern matching 有权
标题翻译：模式匹配
公开(公告)号：US08620940B1
公开(公告)日：2013-12-31
申请号：US12977565
申请日：2010-12-23
申请人： Mathew Hostetter , Kenneth M. Steele , Vijay Aggarwal
发明人： Mathew Hostetter , Kenneth M. Steele , Vijay Aggarwal
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F7/02 , G06F17/30985 , G06F2207/025
摘要： A method for processing data for pattern matching includes: receiving a first sequence of data values; and generating a second sequence of data values based on the first sequence and one or more patterns and history of data values in the first sequence, wherein the second sequence has fewer data values than the first sequence and all subsequences in the first sequence that match at least one of the one or more patterns are represented in the second sequence.
摘要翻译：一种用于处理模式匹配的数据的方法包括：接收第一数据值序列; 以及基于所述第一序列和所述第一序列中的数据值的一个或多个模式和历史来生成第二数据值序列，其中所述第二序列具有比所述第一序列更少的数据值，以及与所述第一序列匹配的所述第一序列中的所有子序列一个或多个图案中的至少一个在第二个序列中表示。

4. 发明授权

US5263161A Non-busy waiting resource control 失效
标题翻译：忙碌等待资源控制
公开(公告)号：US5263161A
公开(公告)日：1993-11-16
申请号：US897590
申请日：1992-06-11
申请人： Paul S. Barth , Richard M. Soley , Kenneth M. Steele
发明人： Paul S. Barth , Richard M. Soley , Kenneth M. Steele
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F9/52 , G06F9/4436
摘要： A data structure has a value field for storing values and a lock field for indicating a lock state of the resource associated with the data structure. This data structure is used to implement a locking protocol amongst multiple processes competing for shared resources. If the lock field is a locked state, the process that locked the lock field has exclusive access to the resource. If, however, the lock field is in an unlocked state, any process may gain access to the resource. The lock field also has deferred states corresponding to the locked and unlocked states wherein multiple requests to lock or unlock the resource may be stored until serviced. The locking protocol is useful in a data processing system having multiple processing elements and utilizes a locking means that includes a local memory controller.
摘要翻译：数据结构具有用于存储值的值字段和用于指示与数据结构相关联的资源的锁定状态的锁定字段。该数据结构用于在多个进程之间实现锁定协议，这些进程竞争共享资源。如果锁定字段为锁定状态，则锁定锁定字段的进程具有对资源的独占访问权限。但是，如果锁定字段处于未锁定状态，任何进程都可以访问资源。锁定域还具有对应于锁定和解锁状态的延迟状态，其中锁定或解锁资源的多个请求可以被存储直到被服务。锁定协议在具有多个处理元件的数据处理系统中是有用的，并且利用包括本地存储器控制器的锁定装置。

5. 发明授权

US08738860B1 Computing in parallel processing environments 有权
标题翻译：在并行处理环境中进行计算
公开(公告)号：US08738860B1
公开(公告)日：2014-05-27
申请号：US13280927
申请日：2011-10-25
申请人： Patrick Robert Griffin , Mathew Hostetter , Anant Agarwal , Chyi-Chang Miao , Christopher D. Metcalf , Bruce Edwards , Carl G. Ramey , Mark B. Rosenbluth , David M. Wentzlaff , Christopher J. Jackson , Ben Harrison , Kenneth M. Steele , John Amann , Shane Bell , Richard Conlin , Kevin Joyce , Christine Deignan , Liewei Bao , Matthew Mattina , Ian Rudolf Bratt , Richard Schooler
发明人： Patrick Robert Griffin , Mathew Hostetter , Anant Agarwal , Chyi-Chang Miao , Christopher D. Metcalf , Bruce Edwards , Carl G. Ramey , Mark B. Rosenbluth , David M. Wentzlaff , Christopher J. Jackson , Ben Harrison , Kenneth M. Steele , John Amann , Shane Bell , Richard Conlin , Kevin Joyce , Christine Deignan , Liewei Bao , Matthew Mattina , Ian Rudolf Bratt , Richard Schooler
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0813 , G06F12/1441
摘要： A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.
摘要翻译：计算系统包括一个或多个核心。每个核心包括处理器。在一些实现中，每个处理器耦合到核心之间的通信网络。在一些实现中，每个核心中的交换机包括交换电路，用于将通过数据路径从其他核到达处理器的数据路径接收的数据转发到其他核心的交换机，并将从处理器接收的数据转发到其他核心的交换机。

6. 发明授权

US08065259B1 Pattern matching in a multiprocessor environment 有权
标题翻译：多处理器环境中的模式匹配
公开(公告)号：US08065259B1
公开(公告)日：2011-11-22
申请号：US12890996
申请日：2010-09-27
申请人： Kenneth M. Steele , Anant Agarwal
发明人： Kenneth M. Steele , Anant Agarwal
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： G06F17/30982 , G06F21/564 , H04L69/16 , H04L69/161 , H04L69/22
摘要： Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible by a first set of one or more processing engines, and storing instructions for matching an input sequence to one or more patterns in memory accessible by a second set of one or more processing engines; distributing information identifying selected input sequences to the first and second sets of processing engines; and retrieving the identified input sequences to perform pattern matching in the first and second sets of processing engines.
摘要翻译：多个互连处理引擎中的模式匹配包括：通过接口接收输入序列流并存储输入序列; 存储用于将输入序列与用于由第一组一个或多个处理引擎访问的存储器中的一个或多个模式进行匹配的指令，以及存储用于将输入序列匹配到存储器中的一个或多个模式的指令，所述存储器可由第二组一个或多个处理发动机; 将识别所选输入序列的信息分发到所述第一和第二组处理引擎; 以及检索所识别的输入序列以在所述第一和第二组处理引擎中执行模式匹配。

7. 发明授权

US07877401B1 Pattern matching 有权
标题翻译：模式匹配
公开(公告)号：US07877401B1
公开(公告)日：2011-01-25
申请号：US11753315
申请日：2007-05-24
申请人： Mathew Hostetter , Kenneth M. Steele , Vijay Aggarwal
发明人： Mathew Hostetter , Kenneth M. Steele , Vijay Aggarwal
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F7/02 , G06F17/30985 , G06F2207/025
摘要： A method for processing data for pattern matching includes: receiving a first sequence of data values; and generating a second sequence of data values based on the first sequence and one or more patterns and history of data values in the first sequence, wherein the second sequence has fewer data values than the first sequence and all subsequences in the first sequence that match at least one of the one or more patterns are represented in the second sequence.
摘要翻译：一种用于处理模式匹配的数据的方法包括：接收第一数据值序列; 以及基于所述第一序列和所述第一序列中的数据值的一个或多个模式和历史来生成第二数据值序列，其中所述第二序列具有比所述第一序列更少的数据值，以及与所述第一序列匹配的所述第一序列中的所有子序列一个或多个图案中的至少一个在第二个序列中表示。

8. 发明授权

US07805392B1 Pattern matching in a multiprocessor environment with finite state automaton transitions based on an order of vectors in a state transition table 有权
标题翻译：基于状态转换表中的向量顺序，在具有有限状态自动机转换的多处理器环境中的模式匹配
公开(公告)号：US07805392B1
公开(公告)日：2010-09-28
申请号：US11564694
申请日：2006-11-29
申请人： Kenneth M. Steele , Anant Agarwal
发明人： Kenneth M. Steele , Anant Agarwal
IPC分类号： G06N5/02
CPC分类号： G06F17/30982 , G06F21/564 , H04L69/16 , H04L69/161 , H04L69/22
摘要： Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible by a first set of one or more processing engines, and storing instructions for matching an input sequence to one or more patterns in memory accessible by a second set of one or more processing engines; distributing information identifying selected input sequences to the first and second sets of processing engines; and retrieving the identified input sequences to perform pattern matching in the first and second sets of processing engines.
摘要翻译：多个互连处理引擎中的模式匹配包括：通过接口接收输入序列流并存储输入序列; 存储用于将输入序列与用于由第一组一个或多个处理引擎访问的存储器中的一个或多个模式进行匹配的指令，以及存储用于将输入序列匹配到存储器中的一个或多个模式的指令，所述指令可由第二组一个或多个处理发动机; 将识别所选输入序列的信息分发到所述第一和第二组处理引擎; 以及检索所识别的输入序列以在所述第一和第二组处理引擎中执行模式匹配。

9. 发明授权

US4696604A Pile assembly for an offshore structure 失效
标题翻译：用于海上结构的桩组件
公开(公告)号：US4696604A
公开(公告)日：1987-09-29
申请号：US894547
申请日：1986-08-08
申请人： Lyle D. Finn , Kenneth M. Steele
发明人： Lyle D. Finn , Kenneth M. Steele
IPC分类号： E02B17/02
CPC分类号： E02B17/027 , E02B2017/0039 , E02B2017/0043
摘要： A pile assembly adapted for use in a compliant piled tower. A plurality of drive piles are driven into the ocean floor in a symetric array about a central, substantially vertical axis. A flex pile is secured to the upper end of each drive pile and extends upward to a preselected elevation above the ocean floor. The longitudinal axes of each drive pile flex pile pair are laterally offset from one another with the flex piles also being arranged in symetric array about the central axis. A tie member is provided to restrain the flex piles from lateral motion relative to one another. The tie member serves to balance the moments established by virtue of the eccentric axes of the flex pile drive pile pairs. The use of eccentric axes in the pile assemblies simplifies driving the drive piles, permits the drive piles to be placed relatively far from one another to minimize pile group effects and permits the flex pile to be designed without being constrained by driving considerations.
摘要翻译：适用于顺应堆放塔的桩组件。多个驱动桩在围绕中心的基本竖直的轴线的对称阵列中被驱动到海底。柔性桩被固定到每个驱动桩的上端，并向上延伸到海底以上的预选高度。每个驱动桩柔性桩对的纵向轴线彼此横向偏移，并且挠性桩也围绕中心轴线以对称阵列布置。提供连接构件以限制柔性桩相对于彼此的横向运动。连杆构件用于平衡由柔性桩驱动桩对的偏心轴构成的力矩。在桩组件中使用偏心轴简化了驱动桩的驱动，允许驱动桩相对放置得相对较远，以最小化桩群效应，并允许设计柔性桩而不受驾驶考虑的限制。

10. 发明授权

US08194690B1 Packet processing in a parallel processing environment 有权
标题翻译：并行处理环境中的数据包处理
公开(公告)号：US08194690B1
公开(公告)日：2012-06-05
申请号：US11753325
申请日：2007-05-24
申请人： Kenneth M. Steele , Vijay Aggarwal
发明人： Kenneth M. Steele , Vijay Aggarwal
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/90 , H04L47/52 , H04L47/60
摘要： Packets are processed in a system that comprises a plurality of interconnected processor cores. The system receives packets into one or more queues. The system associates at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate. The system maps a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and based on at least one rate associated with a node not in the set. The packets are processed in one or more processor cores including the mapped processor core according to the hierarchy.
摘要翻译：分组在包括多个互连处理器核心的系统中进行处理。系统将数据包接收到一个或多个队列中。该系统将节点层级中的至少一些节点与至少一个队列以及具有速率的至少一些节点相关联。该系统基于集合中的节点的层级中的级别并且基于与不在集合中的节点相关联的至少一个速率将一个或多个节点的集合映射到处理器核心。分组在一个或多个处理器核心中被处理，包括根据分层结构的映射的处理器核心。

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