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1. 发明申请

US20190149109A1 SINGLE-ENDED TRANS-IMPEDANCE AMPLIFIER (TIA) FOR ULTRASOUND DEVICE 审中-公开
公开(公告)号：US20190149109A1
公开(公告)日：2019-05-16
申请号：US16244934
申请日：2019-01-10
申请人： Amandeep Singh , Kailiang Chen , Tyler S. Ralston
发明人： Amandeep Singh , Kailiang Chen , Tyler S. Ralston
IPC分类号： H03F3/45 , G01N29/24 , G01N29/44 , H03M1/12
CPC分类号： H03F3/45179 , G01N29/2406 , G01N29/44 , G01N29/4463 , G01N29/449 , H03F3/345 , H03F2200/129 , H03F2203/45116 , H03F2203/45524 , H03M1/124 , H03M1/38
摘要： An ultrasound circuit comprising a single-ended trans-impedance amplifier (TIA) is described, The TIA is coupled to an ultrasonic transducer to amplify an electrical signal generated by the ultrasonic transducer in response to receiving an ultrasound signal. The TEA is followed by further processing circuitry configured to filter, amplify, and digitize the signal produced by the TIA.

2. 发明授权

US08035414B2 Asynchronous logic automata 有权
标题翻译：异步逻辑自动机
公开(公告)号：US08035414B2
公开(公告)日：2011-10-11
申请号：US12422979
申请日：2009-04-13
申请人： Neil Gershenfeld , Kailiang Chen , David Allen Dalrymple
发明人： Neil Gershenfeld , Kailiang Chen , David Allen Dalrymple
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： G06F7/388
摘要： A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation.
摘要翻译：与其最近邻居交互的可重配置，电荷节省的异步逻辑元件系列允许设计和实现在位级别而不是功能块级异步的电路。这些元件通过电荷分组（令牌）传递信息，而不是电压。每个单元都是自定时的，配置为互连的单元以传播延迟速度执行，因此不需要硬件非本地连接。异步逻辑元件包括用于与至少一个相邻小区异步通信的一组边缘，每个边缘具有用于从相邻小区接收令牌的输入和用于将输出电荷分组传送到至少一个相邻小区的输出，以及被配置为利用接收的充电分组作为输入进行逻辑运算，并产生反映逻辑运算结果的输出电荷分组。

3. 发明申请

US20100102848A1 Asynchronous Logic Automata 有权
标题翻译：异步逻辑自动机
公开(公告)号：US20100102848A1
公开(公告)日：2010-04-29
申请号：US12422979
申请日：2009-04-13
申请人： Neil Gershenfeld , Kailiang Chen , David Allen Dalrymple
发明人： Neil Gershenfeld , Kailiang Chen , David Allen Dalrymple
IPC分类号： H03K19/173
CPC分类号： G06F7/388
摘要： A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation.
摘要翻译：与其最近邻居交互的可重配置，电荷节省的异步逻辑元件系列允许设计和实现在位级别而不是功能块级异步的电路。这些元件通过电荷分组（令牌）传递信息，而不是电压。每个单元都是自定时的，配置为互连的单元以传播延迟速度执行，因此不需要硬件非本地连接。异步逻辑元件包括用于与至少一个相邻小区异步通信的一组边缘，每个边缘具有用于从相邻小区接收令牌的输入和用于将输出电荷分组传送到至少一个相邻小区的输出，以及被配置为利用接收的充电分组作为输入进行逻辑运算，并产生反映逻辑运算结果的输出电荷分组。

4. 发明申请

US20210088638A1 SYMMETRIC RECEIVER SWITCH FOR ULTRASOUND DEVICES 有权
公开(公告)号：US20210088638A1
公开(公告)日：2021-03-25
申请号：US17025927
申请日：2020-09-18
申请人： Kailiang Chen , Daniel Rea McMahill , Joseph Lutsky , Keith G. Fife , Nevada J. Sanchez
发明人： Kailiang Chen , Daniel Rea McMahill , Joseph Lutsky , Keith G. Fife , Nevada J. Sanchez
IPC分类号： G01S7/52
摘要： Circuitry for an ultrasound device is described. The ultrasound device may include a symmetric switch positioned between a pulser and an ultrasound transducer. The pulser may produce bipolar pulses. The symmetric switch may selectively isolate a receiver from the pulser and the ultrasound transducer during a transmit mode of the device, when the bipolar pulses are provided by the pulser to the ultrasound transducer for transmission, and may selectively permit the receiver to receive signals from the ultrasound transducer during a receive mode. The symmetric switch may be provided with a well switch to remove well capacitances in a signal path of the device.

5. 发明申请

US20190142387A1 ULTRASOUND APPARATUSES AND METHODS FOR FABRICATING ULTRASOUND DEVICES 审中-公开
公开(公告)号：US20190142387A1
公开(公告)日：2019-05-16
申请号：US16192603
申请日：2018-11-15
申请人： Kailiang Chen , Nevada J. Sanchez , Susan A. Alie , Tyler S. Ralston , Jonathan M. Rothberg , Keith G. Fife , Joseph Lutsky
发明人： Kailiang Chen , Nevada J. Sanchez , Susan A. Alie , Tyler S. Ralston , Jonathan M. Rothberg , Keith G. Fife , Joseph Lutsky
IPC分类号： A61B8/08 , H04B11/00
摘要： Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.

6. 发明申请

US20180376253A1 DIFFERENTIAL ULTRASONIC TRANSDUCER ELEMENT FOR ULTRASOUND DEVICES 审中-公开
公开(公告)号：US20180376253A1
公开(公告)日：2018-12-27
申请号：US16016359
申请日：2018-06-22
申请人： Joseph Lutsky , Nevada J. Sanchez , Kailiang Chen , Keith G. Fife , Tyler S. Ralston
发明人： Joseph Lutsky , Nevada J. Sanchez , Kailiang Chen , Keith G. Fife , Tyler S. Ralston
IPC分类号： H04R17/00
摘要： Aspects of the technology described herein relate to ultrasound circuits that employ a differential ultrasonic transducer element, such as a differential micromachined ultrasonic transducer (MUT) element. The differential ultrasonic transducer element may be coupled to an integrated circuit that is configured to operate the differential ultrasonic transducer element in one or more modes of operation, such as a differential receive mode, a differential transmit mode, a single-ended receive mode, and a single-ended transmit mode.

7. 发明申请

US20180360426A1 MULTI-STAGE TRANS-IMPEDANCE AMPLIFIER (TIA) FOR AN ULTRASOUND DEVICE 审中-公开
公开(公告)号：US20180360426A1
公开(公告)日：2018-12-20
申请号：US16011715
申请日：2018-06-19
申请人： Amandeep Singh , Kailiang Chen , Tyler S. Ralston
发明人： Amandeep Singh , Kailiang Chen , Tyler S. Ralston
IPC分类号： A61B8/08 , H03F3/50 , A61B8/00
摘要： An ultrasound circuit comprising a multi-stage trans-impedance amplifier (TIA) is described. The TIA is coupled to an ultrasonic transducer to amplify an electrical signal generated by the ultrasonic transducer in response to receiving an ultrasound signal. The TIA may include multiple stages, at least two of which operate with different supply voltages. The TIA may be followed by further processing circuitry configured to filter, amplify, and digitize the signal produced by the TIA.

8. 发明申请

US20200150252A1 TRANS-IMPEDANCE AMPLIFIER (TIA) FOR ULTRASOUND DEVICES 审中-公开
公开(公告)号：US20200150252A1
公开(公告)日：2020-05-14
申请号：US16678830
申请日：2019-11-08
申请人： Kailiang Chen , Chao Chen , Keith G. Fife
发明人： Kailiang Chen , Chao Chen , Keith G. Fife
IPC分类号： G01S7/52 , H03F3/187 , G01S15/89
摘要： A variable-current trans-impedance amplifier (TIA) for an ultrasound device is described. The TIA may be coupled to an ultrasonic transducer to amplify an output signal of the ultrasonic transducer representing an ultrasound signal received by the ultrasonic transducer. During acquisition of the ultrasound signal by the ultrasonic transducer, one or more current sources in the TIA may be varied. The variable-current trans-impedance amplifier may include multiple stages, including a first stage having N-P transistor pairs configured to receive an input signal and produce a single-ended amplified signal.

9. 发明申请

US20180367111A1 AMPLIFIER WITH BUILT IN TIME GAIN COMPENSATION FOR ULTRASOUND APPLICATIONS 审中-公开
公开(公告)号：US20180367111A1
公开(公告)日：2018-12-20
申请号：US16011755
申请日：2018-06-19
申请人： Amandeep Singh , Kailiang Chen , Tyler S. Ralston
发明人： Amandeep Singh , Kailiang Chen , Tyler S. Ralston
IPC分类号： H03F3/45 , H03M1/12 , B06B1/02 , G01S15/89 , G01S7/523 , G01N29/44
摘要： An ultrasound circuit comprising a trans-impedance amplifier (TIA) with built-in time gain compensation functionality is described. The TIA is coupled to an ultrasonic transducer to amplify an electrical signal generated by the ultrasonic transducer in response to receiving an ultrasound signal. The TIA is, in some cases, followed by further analog and digital processing circuitry.

10. 发明授权

US08692575B2 Asynchronous logic automata 有权
标题翻译：异步逻辑自动机
公开(公告)号：US08692575B2
公开(公告)日：2014-04-08
申请号：US13271179
申请日：2011-10-11
申请人： Neil Gershenfeld , Kailiang Chen , David Allen Dalrymple
发明人： Neil Gershenfeld , Kailiang Chen , David Allen Dalrymple
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： G06F7/388
摘要： A family of self-timed, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level. The elements pass information by means of state tokens, rather than voltages. Each cell is self-timed, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, the edges receiving state tokens from neighboring logic elements and transferring output state tokens to neighboring logic elements, and circuitry configured to perform, when the circuitry inputs contain valid tokens and the circuitry outputs are empty, a logic operation utilizing received tokens as inputs, thereby producing an output token reflecting the result of the logic operation.
摘要翻译：与其最近邻居交互的自定时，电荷节省异步逻辑元件的系列允许在位级异步的电路的设计和实现。元素通过状态令牌而不是电压传递信息。每个单元都是自定时的，因此不需要硬件非本地连接。异步逻辑元件包括用于与至少一个相邻单元进行异步通信的边缘集合，边缘从相邻逻辑元件接收状态令牌并将输出状态令牌传送到相邻逻辑元件，以及电路，其被配置为当电路输入包含有效令牌和电路输出为空，逻辑操作利用接收的令牌作为输入，从而产生反映逻辑运算结果的输出令牌。

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