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1. 发明授权

US4873459A Programmable interconnect architecture 失效
标题翻译：可编程互连体系结构
公开(公告)号：US4873459A
公开(公告)日：1989-10-10
申请号：US195728
申请日：1988-05-18
申请人： Abbas A. El Gamal , Khaled A. El-Ayat , Jonathan W. Greene , Ta-Pen R. Guo , Justin M. Reyneri
发明人： Abbas A. El Gamal , Khaled A. El-Ayat , Jonathan W. Greene , Ta-Pen R. Guo , Justin M. Reyneri
IPC分类号： G01R31/3185 , H03K19/177
CPC分类号： H03K19/17748 , G01R31/318516 , H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/17796
摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segements connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface. A universal function module may be configured to implement the popular logic functions and has a physical layout which is conducive to custom circuit design.
摘要翻译：公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。布线通道包括通过常开的可编程元件连接的布线段，位于要连接的任何两个段的交点处。可以包括感应电路和接线，以允许来自外部接口接口的内部电路节点（如模块输出）的100％可观察性。通用功能模块可以被配置为实现流行的逻辑功能并且具有有利于定制电路设计的物理布局。

2. 发明授权

US4910417A Universal logic module comprising multiplexers 失效
标题翻译：通用逻辑模块包括多路复用器
公开(公告)号：US4910417A
公开(公告)日：1990-03-20
申请号：US293645
申请日：1989-01-05
申请人： Abbas El Gamal , Khaled A. El-Ayat , Jonathan W. Greene , Ta-Pen R. Guo , Justin M. Reyneri
发明人： Abbas El Gamal , Khaled A. El-Ayat , Jonathan W. Greene , Ta-Pen R. Guo , Justin M. Reyneri
IPC分类号： G01R31/3185 , H03K19/177 , H03K19/094
CPC分类号： H03K19/17728 , G01R31/318516 , H03K19/17704
摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface. A universal function module may be configured to implement the popular logic functions and has a physical layout which is conductive to custom circuit design.
摘要翻译：公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。布线通道包括通过常开的可编程元件连接的布线段，所述可编程元件位于要连接的任何两个段的交点处。可以包括感应电路和接线，以允许来自外部接口接口的内部电路节点（如模块输出）的100％可观察性。通用功能模块可以被配置为实现流行的逻辑功能，并且具有对定制电路设计有导通性的物理布局。

3. 发明授权

US5754826A CAD and simulation system for targeting IC designs to multiple fabrication processes 失效
标题翻译： CAD和仿真系统，用于将IC设计定位到多个制造过程
公开(公告)号：US5754826A
公开(公告)日：1998-05-19
申请号：US511172
申请日：1995-08-04
申请人： Abbas El Gamal , David P. Marple , Justin M. Reyneri
发明人： Abbas El Gamal , David P. Marple , Justin M. Reyneri
IPC分类号： G06F17/50 , H01L21/70
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Using the present invention, only a single design and development process needs to be conducted for ICs fabricated using a number of different fabrication processes. In one embodiment of this process, the IC is first designed on a CAD system using a generic Cell Based Architecture (CBA) library. This generic CBA library represents several libraries for different process technologies. The resulting generic design is then simulated and verified using best and worst case timing delays and other parameters which are derived from a combination of the various technologies. Hence, only one design need be created and simulated. Generic design rule and parasitic parameters are then used to optimize the placement and routing of the generic design. The post-layout generic design is then simulated and verified using performance characteristics determined by a combination of the technologies. The accepted, generic post-layout design is then ported for each intended fabrication process to create the mask patterns associated with each fabrication process.
摘要翻译：使用本发明，仅需要对使用多种不同制造工艺制造的IC进行单一的设计和开发过程。在该过程的一个实施例中，IC首先在使用通用的基于单元的架构（CBA）库的CAD系统上设计。该通用CBA库代表用于不同进程技术的多个库。然后使用最佳和最差情况的时序延迟以及从各种技术的组合导出的其他参数来模拟和验证所得通用设计。因此，只需要创建和模拟一个设计。然后通用设计规则和寄生参数用于优化通用设计的布局和路由。然后使用由技术的组合确定的性能特征来模拟和验证后布局通用设计。然后，接受的通用后布图设计移植到每个预期的制造工艺，以创建与每个制造工艺相关联的掩模图案。

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