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    • 1. 发明授权
    • Techniques for detecting coding incompatibilities
    • 检测编码不兼容性的技术
    • US07716642B1
    • 2010-05-11
    • US11120602
    • 2005-05-03
    • Ofer E. MichaelJosef EzraDar S. Efroni
    • Ofer E. MichaelJosef EzraDar S. Efroni
    • G06F9/44
    • G06F11/3624G06F11/3604
    • Described are techniques for detecting incompatibilities. A first contents of a data item is determined in accordance with a first set of conventions associated with a first processor architecture. A second contents of said data item is determined in accordance with a second set of conventions associated with a second processor architecture and including at least one convention that is not included in said first set. An actual difference between the first contents and the second contents is determined. It is determined whether the actual difference is expected. If the actual difference is not expected, the data item is flagged as an incompatibility candidate. Code referencing the data item is examined to determine any coding incompatibilities due to coding dependencies.
    • 描述了检测不兼容性的技术。 根据与第一处理器架构相关联的第一组约定来确定数据项的第一内容。 所述数据项的第二内容根据与第二处理器体系结构相关联的第二组约定来确定,并且包括不包括在所述第一组中的至少一个约定。 确定第一内容和第二内容之间的实际差异。 确定实际差异是否预期。 如果实际的差异是不可预期的,数据项被标记为不兼容的候选者。 检查引用数据项的代码,以确定由于编码依赖性而导致的任何编码不兼容性。
    • 2. 发明授权
    • Software debugging tool
    • 软件调试工具
    • US07401322B1
    • 2008-07-15
    • US09962485
    • 2001-09-25
    • Eli ShagamJosef EzraAvihu Goral
    • Eli ShagamJosef EzraAvihu Goral
    • G06F9/44G06F11/00
    • G06F11/3676
    • In a method for testing computer code, each branch that occurs within the machine-readable code is located. A first tracepoint is placed immediately after the beginning of the branch and a second tracepoint at the target address of each branch, each tracepoint generating an indicator. When the machine-readable code with the tracepoints is executed on the target computer, the method identifies those indicators that have been generated by their corresponding tracepoints, thereby permitting determination of those branches that the program control flow has not passed through. The test cases are modified to exercise the previously omitted branches, and the converted code is re-executed, until all branches have been properly exercised. The tracepoints are automatically eliminated after they have performed their intended function.
    • 在用于测试计算机代码的方法中,位于机器可读代码内的每个分支都位于该位置。 在分支开始之后立即放置第一个跟踪点,并在每个分支的目标地址处放置第二个跟踪点,每个跟踪点生成一个指示符。 当在目标计算机上执行具有跟踪点的机器可读代码时,该方法识别由其相应跟踪点生成的那些指示符,从而允许确定程序控制流未通过的那些分支。 修改测试用例以执行先前省略的分支,并重新执行转换后的代码,直到所有分支都已正确运行。 跟踪点在执行预定功能后自动消除。
    • 4. 发明授权
    • Method for cache management for positioning cache slot
    • 缓存管理定位缓存槽的方法
    • US07143393B1
    • 2006-11-28
    • US10178085
    • 2002-06-24
    • Josef EzraDaniel Lambright
    • Josef EzraDaniel Lambright
    • G06F9/44G06F12/00
    • G06F12/0871G06F12/084G06F12/12Y10S707/99931
    • Described are techniques used in connection with cache management. Data included in a cache slot is put “on parole” with a first cache hit while waiting for subsequent cache hits. If a subsequent hit is received to the cache slot, it remains in the cache for a longer time period than a slot having only a first cache hit. The cache may be organized as a plurality of memory banks of cache slots. Each memory bank has an associated control slot that includes groups of extents of tags. Each cache slot has a corresponding tag, and a time stamp. The time stamp of slots in the cache may be adjusted affecting the amount of time a particular portion of data remains in the cache.
    • 描述了与高速缓存管理有关的技术。 包含在缓存插槽中的数据在等待后续缓存命中时被放置在“假释”上,并带有第一个缓存命中。 如果随后的命中被接收到高速缓存时隙,则其在高速缓存中保持比仅具有第一高速缓存命中的时隙更长的时间段。 高速缓存可以被组织为高速缓存槽的多个存储器组。 每个存储体具有包括标签区段组的相关控制槽。 每个缓存槽具有相应的标签和时间戳。 可以调整高速缓存中的时隙的时间戳影响数据的特定部分保留在高速缓存中的时间量。
    • 6. 发明授权
    • Private slot
    • 私人插槽
    • US08082397B1
    • 2011-12-20
    • US10955136
    • 2004-09-30
    • Josef EzraAdi Ofer
    • Josef EzraAdi Ofer
    • G06F12/02
    • G06F12/084
    • Described are techniques and criteria used in connection with cache management. The cache may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associated control slot that includes groups of extents of tags. Each cache slot has a corresponding tag that includes a bit value indicating the availability of the associated cache slot, and a time stamp indicating the last time the data in the slot was used. The cache may be shared by multiple processors. Exclusive access of the cache slots is implemented using an atomic compare and swap instruction. The time stamp of slots in the cache may be adjusted to indicate ages of slots affecting the amount of time a particular portion of data remains in the cache. Each director may obtain a cache slot from a private stack of nondata cache slots in addition to accessing a shared cache used by all directors.
    • 描述了与缓存管理相关联使用的技术和标准。 高速缓存可以被组织为多个存储体,其中每个存储体包括多个时隙。 每个存储体具有包括标签区段组的相关控制槽。 每个高速缓存槽具有包括指示相关高速缓存槽的可用性的位值的对应标签,以及指示使用槽中的数据的最后时间的时间戳。 高速缓存可以由多个处理器共享。 使用原子比较和交换指令实现高速缓存槽的独占访问。 可以调整高速缓存中的时隙的时间戳以指示影响特定部分数据保留在高速缓存中的时间量的时隙的年龄。 除了访问所有董事使用的共享缓存之外,每个董事可以从非数据缓存槽的私有堆栈获得高速缓存槽。
    • 8. 发明授权
    • Method and apparatus for controlling exclusive access to a shared resource in a data storage system
    • 用于控制对数据存储系统中的共享资源的独占访问的方法和装置
    • US07246187B1
    • 2007-07-17
    • US10955033
    • 2004-09-30
    • Josef EzraAdi Ofer
    • Josef EzraAdi Ofer
    • G06F12/14
    • G06F12/084G06F9/526
    • A method for controlling exclusive access to a resource shared by multiple processors in a data storage system includes providing a system lock procedure to permit a processor to obtain a lock on the shared resource preventing other processors from accessing the shared resource and providing a faked lock procedure to indicate to the system lock procedure that a processor has a lock on the shared resource where such a lock does not exist, and wherein the faked lock procedure prevents another processor from obtaining the lock on the shared resource, but does not prevent other processors from accessing the shared resource. A data storage system according to the invention includes a shared resource, a plurality of processors coupled to the shared resource through a communication channel, and a lock services procedure providing the system lock procedure and the faked lock procedure. In one embodiment, the shared resource is a cache and the system lock procedure permits a processor to lock the entire cache whereas the faked lock procedure is implemented by a processor seeking exclusive access of a cache slot.
    • 用于控制对数据存储系统中的多个处理器共享的资源的独占访问的方法包括提供系统锁定过程以允许处理器获得共享资源上的锁定,防止其他处理器访问共享资源并提供伪造的锁定过程 为了向系统锁定过程指示处理器对不存在这样的锁的共享资源上的锁定,并且其中伪造的锁程序防止另一个处理器获得共享资源上的锁定,但是不阻止其他处理器 访问共享资源。 根据本发明的数据存储系统包括共享资源,通过通信信道耦合到共享资源的多个处理器,以及提供系统锁定过程和假锁定过程的锁定服务过程。 在一个实施例中,共享资源是高速缓存,并且系统锁定过程允许处理器锁定整个高速缓存,而假的锁定过程由寻求高速缓存槽的独占访问的处理器来实现。
    • 9. 发明授权
    • Locally buffered cache extensions having associated control parameters to determine use for cache allocation on subsequent requests
    • 具有相关控制参数的本地缓冲缓存扩展,以确定对后续请求的高速缓存分配的使用
    • US07089357B1
    • 2006-08-08
    • US10667564
    • 2003-09-22
    • Josef Ezra
    • Josef Ezra
    • G06F12/00G06F13/00
    • G06F12/123G06F12/0866
    • A method and apparatus for cache management in a data storage system is presented. A table with tags corresponding to cache slots in a cache memory is provided. A copy of the table is stored in a local buffer in response to a request for allocation of one of the cache slots. The locally buffered table is used to make the requested cache slot allocation. A set of control parameters associated with the locally buffered table is used to determine if the locally buffered table can be re-used for cache slot allocation in response to a subsequent request for cache slot allocation. User-selectable levels are provided to control the degree of locally buffered table re-use. The user-selectable levels determine which values of the control parameters are used.
    • 提出了一种数据存储系统中缓存管理的方法和装置。 提供了具有与缓存存储器中的高速缓存槽相对应的标签的表。 响应于对一个缓存时隙的分配的请求,将表的副本存储在本地缓冲器中。 本地缓冲表用于进行请求的高速缓存时隙分配。 使用与本地缓冲表相关联的一组控制参数来确定本地缓冲表是否可以被重新用于响应于对高速缓存时隙分配的后续请求的高速缓存时隙分配。 提供用户可选择的级别来控制本地缓冲表重用的程度。 用户可选择的级别确定使用控制参数的哪些值。
    • 10. 发明授权
    • Cache management via statistically adjusted slot aging
    • 通过统计调整的时隙老化进行缓存管理
    • US06594742B1
    • 2003-07-15
    • US09850551
    • 2001-05-07
    • Josef Ezra
    • Josef Ezra
    • G06F1200
    • G06F12/123G06F12/0866G06F2212/6042
    • The invention features a method and a system for selecting a slot within a memory unit, e.g., cache, for removal. The memory unit is accessible to a plurality of processors, and each slot in the memory unit has a corresponding entry in an age table. Each time when a processor examines one of the entries, an age value of the entry is increased. When the age value is above a maturity age, the corresponding slot becomes a removable slot. Each processor also maintains statistics to estimate the number of removable slots in the memory unit. According to the statistics, adjusts a maturity age associated with the processor dynamically and independently to control the number of removable slots. Accordingly, the number removable slots can be maintained at a pre-determined percentage relative to the total number of slots in the memory unit.
    • 本发明的特征在于一种用于选择存储器单元(例如,高速缓存)中的时隙以用于移除的方法和系统。 存储器单元可被多个处理器访问,并且存储器单元中的每个时隙在年龄表中具有相应的条目。 每当处理器检查其中一个条目时,条目的年龄值将增加。 当年龄高于成熟年龄时,相应的插槽将成为可移动插槽。 每个处理器还维护统计信息以估计存储器单元中的可移动插槽的数量。 根据统计,动态和独立地调整与处理器相关联的成熟期以控制可移动插槽的数量。 因此,相对于存储器单元中的时隙总数,可以将数量可移动时隙保持在预定百分比。