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    • 6. 发明授权
    • Monolithically integrated E/D mode HEMT and method for fabricating the same
    • 单片集成E / D模式HEMT及其制造方法
    • US06670652B2
    • 2003-12-30
    • US10088793
    • 2002-03-22
    • Jong-In Song
    • Jong-In Song
    • H01L310328
    • H01L27/0605H01L21/8252
    • The monolithically integrated Enhancement/Depletion mode HEMT (high-electron-mobility transistor) of the present invention comprises: a buffer layer, a channel layer, a spacer layer, a first barrier layer, a second barrier layer, a third barrier layer, and an ohmic layer consecutively formed on a semiconductor substrate from bottom to top; the first exposed region (a gate region for a Depletion-mode HEMT) formed by selective etching of the ohmic layer to expose the third barrier layer; a second exposed region (a gate region for an Enhancement-mode HEMT) formed by selective etchings of the ohmic layer and the third barrier layer to expose the second barrier layer; and gate electrodes formed on the first and second exposed gate regions. According to the present invention, a monolithically integrated Enhancement/Depletion mode HEMT having a uniform threshold voltage can easily be fabricated. The second barrier layer, which has a larger bandgap energy compared with those of other barrier layers and is used for the fabrication of an Enhancement-mode HEMT, plays a role of increasing the potential barrier height with respect to the gate electrode metal. The increased potential barrier height can make the total thickness of barrier layers required for the threshold voltage of the Enhancement-mode HEMT device thicker than that of a conventional Enhancement-mode HEMT. This improves the speed characteristic of the Enhancement-mode HEMT since the transistor has a decreased gate capacitance.
    • 本发明的单片集成的增强/消耗模式HEMT(高电子迁移率晶体管)包括:缓冲层,沟道层,间隔层,第一势垒层,第二阻挡层,第三阻挡层和 从底部到顶部连续地形成在半导体衬底上的欧姆层; 通过选择性蚀刻欧姆层以暴露第三阻挡层形成的第一曝光区域(用于耗尽型HEMT的栅极区域); 通过欧姆层和第三阻挡层的选择性蚀刻形成的暴露第二阻挡层的第二曝光区域(用于增强型HEMT的栅极区域); 以及形成在第一和第二暴露栅极区上的栅电极。 根据本发明,可以容易地制造具有均匀阈值电压的单片集成增强/耗尽模式HEMT。 与其它阻挡层的能隙相比具有更大的带隙能量并且用于制造增强型HEMT的第二阻挡层起到增加相对于栅电极金属的势垒高度的作用。 增加的势垒高度可以使增强型HEMT器件的阈值电压所需的势垒层的总厚度比常规增强型HEMT的阈值电压的总厚度更厚。 这提高了增强型HEMT的速度特性,因为晶体管具有降低的栅极电容。