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1. 发明申请

US20130058404A1 METHOD OF MOTION PREDICTION OF MULTIMEDIA VIDEO CODING 审中-公开
标题翻译：多媒体视频编码运动预测方法
公开(公告)号：US20130058404A1
公开(公告)日：2013-03-07
申请号：US13223469
申请日：2011-09-01
申请人： Jiun-In GUO , Ching-Lung Su , Hsiang-Chieh Kao
发明人： Jiun-In GUO , Ching-Lung Su , Hsiang-Chieh Kao
IPC分类号： H04N7/26
CPC分类号： H04N19/33 , H04N19/103 , H04N19/136 , H04N19/176 , H04N19/52
摘要： A method of motion prediction of multimedia video coding includes the steps of a) defining that each of macroblocks of enhancement layers has corresponding BL_Residual, EL_Residual, and EL_ResidualME; b) acquiring the BL_Residual that the current macroblock corresponds to from one of the enhancement layers; c) identifying whether the BL_Residual is zero; if it is zero, apply the motion prediction of video coding to the current layer and then proceed to the step e); if it is not zero, proceed to the next step d); d) comparing the BL_Residual that the current macroblock corresponds to with a threshold; if the BL_Residual is smaller than the threshold, apply the motion prediction of video coding to the current layer; if the BL_Residual is bigger than the threshold, proceed to cross-layer-mode motion prediction of video coding; and e) ending.
摘要翻译：多媒体视频编码的运动预测方法包括以下步骤：a）确定增强层的每个宏块具有相应的BL_Residual，EL_Residual和EL_ResidualME; b）从一个增强层获取当前宏块对应的BL_Residual; c）识别BL_Residual是否为零; 如果为零，则将视频编码的运动预测应用于当前层，然后进行步骤e）; 如果不为零，则进行下一步骤d）; d）将当前宏块对应的BL_Residual与阈值进行比较; 如果BL_Residual小于阈值，则将视频编码的运动预测应用到当前层; 如果BL_Residual大于阈值，则进行视频编码的跨层模式运动预测; 和e）结束。

2. 发明申请

US20110019018A1 Image comprssion system in coordination with camera motion 审中-公开
标题翻译：图像压缩系统与摄像机运动协调
公开(公告)号：US20110019018A1
公开(公告)日：2011-01-27
申请号：US12458752
申请日：2009-07-22
申请人： Shi-Wu Lo , Jiun-In Guo , Tzu-Chun Chang
发明人： Shi-Wu Lo , Jiun-In Guo , Tzu-Chun Chang
IPC分类号： H04N7/12 , H04N5/228
CPC分类号： H04N5/23248 , H04N5/23258 , H04N19/513 , H04N19/533 , H04N19/61
摘要： An image compression system in coordination with camera motion includes a camera for capturing motion pictures; a motion detection device structurally connected with the camera for detecting motions of the camera; an image compression electrically connected with the camera for compressing the motion pictures; and a motion vector receiver electrically connected with the motion diction device and the image compression device for receiving motion signals generated by the motions and then transmitting the motion signals to the image compression device, whereby the image compression device can refer to the motion signals for calculation while compressing the motion pictures. Accordingly, the image compression system can compress the images in coordination with the camera motion and meanwhile eliminate the minor vibrations in the images.
摘要翻译：与相机运动协调的图像压缩系统包括用于拍摄动态影像的相机; 与所述照相机结构地连接以检测所述照相机的运动的运动检测装置; 与照相机电连接以压缩运动图像的图像压缩; 以及运动矢量接收器，与动静词装置和图像压缩装置电连接，用于接收由运动产生的运动信号，然后将运动信号发送到图像压缩装置，由此图像压缩装置可以参考用于计算的运动信号同时压缩动态影像。因此，图像压缩系统可以与摄像机运动协调地压缩图像，同时消除图像中的微小振动。

3. 发明申请

US20080225939A1 MULTIFUNCTIONAL VIDEO ENCODING CIRCUIT SYSTEM 审中-公开
标题翻译：多功能视频编码电路系统
公开(公告)号：US20080225939A1
公开(公告)日：2008-09-18
申请号：US11686571
申请日：2007-03-15
申请人： JIUN-IN GUO , KUAN-HUNG CHEN , JINN-SHYAN WANG , YU-MIN CHEN , YUAN-SUN CHU
发明人： JIUN-IN GUO , KUAN-HUNG CHEN , JINN-SHYAN WANG , YU-MIN CHEN , YUAN-SUN CHU
IPC分类号： H04B1/66
CPC分类号： H04N19/43 , H04N19/42
摘要： The present invention discloses a multifunctional video encoding circuit system capable of performing six types of operations: addition, subtraction, multiplication, multiply-accumulation, interpolation, and absolute difference summation. A partial product generation part, a partial product reduction part and an accumulation part of the circuit system are equipped with a virtual power suppression unit each for reducing the power consumption of the partial product generation part, the partial product reduction part and the accumulation part, so as to reduce the power consumption of the multifunctional video encoding circuit system.
摘要翻译：本发明公开了一种能够进行加法，减法，乘法，乘法累积，插补和绝对差分求和的六种操作的多功能视频编码电路系统。部分产品生成部分，部分产品减少部分和电路系统的累积部分配备有虚拟功率抑制单元，每个虚拟功率抑制单元用于降低部分产品生成部分，部分产品减少部分和累积部分的功耗，从而降低多功能视频编码电路系统的功耗。

4. 发明申请

US20080063047A1 Intra prediction circuit device applied to the H.264 video coding standard 有权
标题翻译：帧内预测电路设备应用于H.264视频编码标准
公开(公告)号：US20080063047A1
公开(公告)日：2008-03-13
申请号：US11517348
申请日：2006-09-08
申请人： Jiun-In Guo , Jinn-Shyan Wang , Jia-Wei Chen
发明人： Jiun-In Guo , Jinn-Shyan Wang , Jia-Wei Chen
IPC分类号： H04B1/66
CPC分类号： H04N19/42 , H04N19/11 , H04N19/176 , H04N19/61
摘要： An intra prediction circuit device applied to the H.264 video coding standard is provided. The intra prediction device uses a method of decreasing the repeated operations of the shared terms of the video pixel data to reduce the circuit computation and simplify the hardware architecture. In the intra prediction scheme, the computational complexity can be lessened by implementing not only the adder based method but also decomposition technique to simplify the algorithm of the intra prediction.
摘要翻译：提供了应用于H.264视频编码标准的帧内预测电路装置。帧内预测装置使用减少视频像素数据的共享项的重复操作以减少电路计算并简化硬件体系结构的方法。在帧内预测方案中，通过不仅采用基于加法器的方法，而且通过实现分解技术来简化帧内预测算法，可以减少计算复杂度。

5. 发明授权

US07117236B2 Parallel adder-based DCT/IDCT design using cyclic convolution 有权
标题翻译：基于并行加法器的DCT / IDCT设计采用循环卷积
公开(公告)号：US07117236B2
公开(公告)日：2006-10-03
申请号：US10897486
申请日：2004-07-23
申请人： Jiun-In Guo , Kun-Wang Liu
发明人： Jiun-In Guo , Kun-Wang Liu
IPC分类号： G06F7/14
CPC分类号： G06F7/76 , G06F17/147
摘要： The present invention provides a device and method for applying 1-D and 2-D DCT and IDCT transforms to sets of input data, typically 8×8 or 16×16 matricies of coefficients. In one embodiment, the present invention provides input lines, logic to pre-add input values and generate operands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform. The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the present invention may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic to pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.
摘要翻译：本发明提供一种用于将1-D和2-D DCT和IDCT变换应用于输入数据集合（通常为8×8或16×16系数矩阵）的装置和方法。在一个实施例中，本发明提供输入线，用于预先添加输入值并产生操作数的逻辑，以及有效地执行应用DCT / IDCT变换所需的相乘运算的一个或多个加法器网络。该设备可以应用1-D变换两次来完成2-D变换。或者，本发明可以包括用于第二个1-D变换的连续的逻辑级，或者可以将通过相同的逻辑转换的数据一次发送到用于第二个1-D变换的预加和加法网络。计算可以在布尔编码操作数后进行。该处理可以在生成输出值之和的向量和产生v N n N之间进行分割，输出值的差异向量可以被重新组合以产生输出向量v。

6. 发明授权

US08111756B2 Method for reducing computational complexity of video compression standard 有权
标题翻译：降低视频压缩标准计算复杂度的方法
公开(公告)号：US08111756B2
公开(公告)日：2012-02-07
申请号：US11512287
申请日：2006-08-30
申请人： Jiun-In Guo , Jinn-Shyan Wang , Jia-Wei Chen , Chun-Hao Chang , Yi-Huan Ou Yang , Chien-Chang Lin
发明人： Jiun-In Guo , Jinn-Shyan Wang , Jia-Wei Chen , Chun-Hao Chang , Yi-Huan Ou Yang , Chien-Chang Lin
IPC分类号： H04N7/12
CPC分类号： H04N19/11 , H04N19/176
摘要： A method for reducing computational complexity of video compression standard is provided, and it includes an intra 4×4 macroblock (I4MB) search algorithm, an intra 16×16 macroblock (I16MB) search algorithm and a chroma search algorithm. The I4MB search algorithm and I16MB search algorithm accelerate the prediction process of the luma macroblock, and the chroma search algorithm accelerates the prediction process of chroma macroblock. The above algorithms can greatly reduce the computation of prediction mode of video compression standard.
摘要翻译：提供了一种降低视频压缩标准计算复杂度的方法，包括内部4×4宏块（I4MB）搜索算法，帧内16×16宏块（I16MB）搜索算法和色度搜索算法。 I4MB搜索算法和I16MB搜索算法加速了亮度宏块的预测过程，色度搜索算法加速了色度宏块的预测过程。上述算法可以大大减少视频压缩标准预测模式的计算。

7. 发明申请

US20110110430A1 METHOD FOR MOTION ESTIMATION IN MULTIMEDIA IMAGES 审中-公开
标题翻译：多媒体图像运动估计方法
公开(公告)号：US20110110430A1
公开(公告)日：2011-05-12
申请号：US12908124
申请日：2010-10-20
申请人： JIUN-IN GUO , CHING-LUNG SU , CHANG-HUNG TSAI , HSIN-YI LI
发明人： JIUN-IN GUO , CHING-LUNG SU , CHANG-HUNG TSAI , HSIN-YI LI
IPC分类号： H04N7/26
CPC分类号： H04N19/176 , H04N19/436 , H04N19/513 , H04N19/56 , H04N19/57
摘要： The present invention relates to a method for motion estimation in multimedia images, which comprises steps of: dividing a predict image frame into a plurality of groups of macroblocks, and each of the groups of macroblocks including a plurality of macroblocks; predicting a motion vector of each of the groups of macroblocks, and producing a predict motion vector; producing one or more search windows according to the predict motion vector; and comparing a plurality of pixels in each macroblock of each group of macroblocks to a plurality of pixels in the search window, and producing an actual motion vector, respectively. Thereby, by gathering a plurality of macroblocks, a shared predict motion vector is produced for reducing computations in coding. Hence, the coding efficiency can be enhanced.
摘要翻译：多媒体图像中的运动估计方法技术领域本发明涉及一种多媒体图像中的运动估计方法，包括以下步骤：将预测图像帧划分成多组宏块，并且每个宏块组包括多个宏块; 预测每个宏块组的运动矢量，并产生预测运动矢量; 根据预测运动矢量产生一个或多个搜索窗口; 以及将每个宏块组中的每个宏块中的多个像素与搜索窗口中的多个像素进行比较，并分别产生实际的运动矢量。因此，通过收集多个宏块，产生共享预测运动矢量以减少编码中的计算。因此，可以提高编码效率。

8. 发明申请

US20100104010A1 REAL-TIME RATE-CONTROL METHOD FOR VIDEO ENCODER CHIP 审中-公开
标题翻译：视频编码器芯片的实时速率控制方法
公开(公告)号：US20100104010A1
公开(公告)日：2010-04-29
申请号：US12494113
申请日：2009-06-29
申请人： Jiun-In GUO , Ping-Tsung Wu , Tzu-Chun Chang , Ching-Lung Su
发明人： Jiun-In GUO , Ping-Tsung Wu , Tzu-Chun Chang , Ching-Lung Su
IPC分类号： H04N7/26
CPC分类号： H04N19/198 , H04N19/115 , H04N19/126 , H04N19/14 , H04N19/149 , H04N19/152 , H04N19/17 , H04N19/172 , H04N19/176 , H04N19/196 , H04N19/197 , H04N19/423 , H04N19/43 , H04N19/61
摘要： The present invention discloses a real-time rate-control method for a video encoder chip, wherein a BU-based RC algorithm is realized in a pipeline architecture, and wherein the RC algorithm is divided into an UpdateQP part arranged before the IME stage and an UpdateModel part arranged behind the entropy stage. When a currently processed frame contains a plurality of macro blocks, the bits used by several leading macro blocks and the remaining bits are predicted. Only the average value of the MADs of the preceding frame is stored in the memory. Thereby, memory consumption is greatly reduced, and quantization parameters are obtained to predict the bit number required by the next frame. The present invention further defines a region of interest and automatically regulates the bit distribution ratio thereof to enhance the sharpness thereof.
摘要翻译：本发明公开了一种用于视频编码器芯片的实时速率控制方法，其中在流水线架构中实现基于BU的RC算法，并且其中所述RC算法被划分为在IME阶段之前排列的UpdateQP部分和 UpdateModel部分安排在熵阶段之后。当当前处理的帧包含多个宏块时，预测由几个前导宏块使用的位和剩余的位。只有前一帧的MAD的平均值存储在存储器中。从而，大大减少了存储器消耗，并且获得量化参数来预测下一帧所需的位数。本发明进一步限定感兴趣的区域并自动调节其比特分配比率以增强其清晰度。

9. 发明申请

US20080062019A1 DEVICE FOR VIDEO DECODING 有权
标题翻译：用于视频解码的设备
公开(公告)号：US20080062019A1
公开(公告)日：2008-03-13
申请号：US11519922
申请日：2006-09-13
申请人： Jiun-In Guo , Yao-Chang Yang
发明人： Jiun-In Guo , Yao-Chang Yang
IPC分类号： H03M7/00
CPC分类号： H04N19/42 , H04N19/13 , H04N19/61
摘要： A device for video decoding is disclosed. It includes at least a pipeline scheduler, a decoding core, a segmented context memory and a context cache. The pipeline scheduler and the decoding core could decrease the time taken in a code-decoding period. The segmented context memory and the context cache could reduce accessing time of reading and writing context values.
摘要翻译：公开了一种用于视频解码的设备。它至少包括流水线调度器，解码核心，分段上下文存储器和上下文高速缓存。流水线调度器和解码核心可以减少码译码周期所花费的时间。分段上下文存储器和上下文高速缓存可以减少读取和写入上下文值的访问时间。

10. 发明授权

US06871208B1 Parallel adder-based DCT/IDCT design using cyclic convolution 有权
标题翻译：基于并行加法器的DCT / IDCT设计采用循环卷积
公开(公告)号：US06871208B1
公开(公告)日：2005-03-22
申请号：US09452655
申请日：1999-12-01
申请人： Jiun-In Guo , Kun-Wang Liu
发明人： Jiun-In Guo , Kun-Wang Liu
IPC分类号： G06F17/14
CPC分类号： G06F7/76 , G06F17/147
摘要： A device and method are described that apply 1-D and 2-D discrete cosine transforms (DCT) and inverse discrete cosine transforms (IDCT) to sets of input data, typically 8×8 or 16×16 matricies of coefficients. One device includes input lines, logic to pre-add input values and generate opcrands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform. The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the device may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic or pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.
摘要翻译：描述了将1-D和2-D离散余弦变换（DCT）和反相离散余弦变换（IDCT）应用于输入数据集合（通常为8×8或16×16系数系数）的装置和方法。一个设备包括输入线，用于预先添加输入值并生成opcrand的逻辑，以及有效地执行应用DCT / IDCT变换所需的乘法运算的一个或多个加法器网络。该设备可以应用1-D变换两次来完成2-D变换。或者，设备可以包括用于第二个1-D变换的连续的逻辑级，或者它可以通过用于第二个1-D变换的相同的逻辑或预加和加法器网络发送一次转换的数据。计算可以在布尔编码操作数后进行。可以在产生vp，输出值之和的矢量和产生vn，输出值差的向量之间分割处理，该向量可以被重组以产生输出向量v。

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