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1. 发明授权

US09688558B2 Apparatus for concentration reaction of carbon dioxide using magnesium ions in seawater, and method for sequestrating carbon dioxide in ocean using same 有权
公开(公告)号：US09688558B2
公开(公告)日：2017-06-27
申请号：US14412636
申请日：2012-08-14
申请人： Jung Hyun Lee , Jin Hyeok Choi , Joon Woo Gil
发明人： Jung Hyun Lee , Jin Hyeok Choi , Joon Woo Gil
IPC分类号： C02F9/00 , B01D53/62 , C02F1/20 , C02F1/70 , C02F1/52 , C02F101/10 , C02F103/02 , C02F103/08 , C02F103/12 , C02F103/16
CPC分类号： C02F9/00 , B01D53/62 , B01D2251/402 , B01D2252/1035 , B01D2257/504 , C02F1/20 , C02F1/5236 , C02F1/70 , C02F2101/10 , C02F2103/02 , C02F2103/08 , C02F2103/12 , C02F2103/16 , Y02C10/04
摘要： A method for sequestrating carbon dioxide in the ocean of the present invention coverts carbon dioxide into a high concentration of bicarbonate ions by using a neutralization method using calcium oxide commonly contained in alkaline industrial waste, prepares elution water for stably containing bicarbonate ions even when making contact with the atmosphere through aeration, and discharges the elution water into an area of the ocean of a relatively shallow depth to sequestrate carbon dioxide. According to the present invention, the present invention is a carbon dioxide storage method which uses alkaline industrial waste to carry out carbon dioxide ocean sequestration at relatively low cost, and can sequestrate carbon dioxide for a long time while minimizing bad environmental influences such as ocean acidification and the like, and is thus environmentally friendly. Therefore, it is possible to actively respond to carbon dioxide emission restrictions and simultaneously achieve economical efficiency by securing certified emission reductions henceforth.

2. 发明授权

US08281064B2 Systems, methods and computer program products for encoding data to be written to a nonvolatile memory based on wear-leveling information 有权
标题翻译：用于基于磨损均衡信息编码要写入非易失性存储器的数据的系统，方法和计算机程序产品
公开(公告)号：US08281064B2
公开(公告)日：2012-10-02
申请号：US12410150
申请日：2009-03-24
申请人： Hwa-Seok Oh , Jin-Hyeok Choi
发明人： Hwa-Seok Oh , Jin-Hyeok Choi
IPC分类号： G06F12/00
CPC分类号： G11C11/5628 , G11C16/349 , G11C29/00 , G11C2211/5647
摘要： A nonvolatile memory system is operated by providing data to be written to a nonvolatile memory, logically combining the data to be written to the nonvolatile memory with a random pattern to generate encoded data; and programming the encoded data in the nonvolatile memory.
摘要翻译：通过提供要写入非易失性存储器的数据来操作非易失性存储器系统，将要写入非易失性存储器的数据以随机模式逻辑组合以产生编码数据; 并将编码数据编程在非易失性存储器中。

3. 发明授权

US08187768B2 Separating plate of solid oxide fuel cell stack 有权
标题翻译：固体氧化物燃料电池堆分离板
公开(公告)号：US08187768B2
公开(公告)日：2012-05-29
申请号：US12607491
申请日：2009-10-28
申请人： Tae-Hee Lee , Young-Sung Yoo , Jin-Hyeok Choi
发明人： Tae-Hee Lee , Young-Sung Yoo , Jin-Hyeok Choi
IPC分类号： H01M4/64 , H01M2/14 , H01M2/18
CPC分类号： H01M8/0273 , H01M8/0258 , H01M8/0263 , H01M8/0265 , H01M8/0271 , H01M2008/1293
摘要： The present invention relates to a separating plate of solid oxide fuel cell stack. The separating plate of solid oxide fuel cell stack includes a substrate, upper and lower micro channel plates and upper and lower sealing guides. The substrate includes a fuel inflow/outflow manifold and an air inflow/outflow manifold disposed opposing to each other in a diagonal direction, a fuel channel having a pair of horizontal channels and an inclined channel connecting ends of the horizontal channels so as to connect the fuel inflow/outflow manifold, and an air channel having a pair of vertical channels and an inclined channel connecting ends of the vertical channels so as to connect the air inflow/outflow manifold. The upper and lower micro channel plates are attached to upper and lower parts of the substrate and includes a plurality of micro channels so as to distribute uniformly fuel flowing in the fuel channel and air flowing in the air channel. The upper and lower sealing guides keep a constant gap with the upper and lower micro channel plates and are attached to the upper and lower parts of the substrate.
摘要翻译：本发明涉及一种固体氧化物燃料电池堆的分离板。固体氧化物燃料电池堆的分离板包括基板，上下微通道板和上下密封引导件。基板包括燃料流入/流出歧管和沿对角线方向彼此相对布置的空气流入/流出歧管，具有一对水平通道的燃料通道和连接水平通道的端部的倾斜通道，以便连接燃料流入/流出歧管，以及具有一对垂直通道的空气通道和连接垂直通道端部的倾斜通道，以连接空气流入/流出歧管。上下微通道板附接到基板的上部和下部，并且包括多个微通道，以便均匀地分布在燃料通道中流动的燃料和在空气通道中流动的空气。上下密封引导件与上下微通道板保持恒定的间隙，并附接到基板的上部和下部。

4. 发明授权

US08166230B2 Memory systems and methods of initializing the same 有权
标题翻译：内存系统和初始化方法
公开(公告)号：US08166230B2
公开(公告)日：2012-04-24
申请号：US12353403
申请日：2009-01-14
申请人： Jin-Hyeok Choi , Sung-Hoon Lee , Si-Hoon Hong , Tae-Keun Jeon
发明人： Jin-Hyeok Choi , Sung-Hoon Lee , Si-Hoon Hong , Tae-Keun Jeon
IPC分类号： G06F13/00 , G06F13/28 , G06F9/00
CPC分类号： G06F12/0646
摘要： A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access each memory card using the default RCA, and to change the default RCA to a unique RCA upon each sequential access.
摘要翻译：提供了一种存储器系统，包括主处理器和连接到主处理器的多个级联连接的存储卡。每个存储卡在存储器系统的初始化之前存储相同的默认相对卡地址（RCA）。主处理器配置为使用默认RCA顺序访问每个存储卡，并且在每次顺序访问时将默认RCA更改为唯一的RCA。

5. 发明授权

US07602642B2 Nonvolatile memory system and associated programming methods 有权
标题翻译：非易失性存储器系统和相关编程方法
公开(公告)号：US07602642B2
公开(公告)日：2009-10-13
申请号：US11730322
申请日：2007-03-30
申请人： Jin-Hyeok Choi
发明人： Jin-Hyeok Choi
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G06F11/1072 , G11C11/5628 , G11C16/3454 , G11C29/76 , G11C2029/0409 , G11C2029/0411 , G11C2211/5642 , G11C2211/5643
摘要： A nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells. The memory controller includes a backup memory adapted to store a backup copy of previously programmed data from the multi-level flash memory cells when further programming of the multi-level flash memory cells fails. The backup copy of the previously programmed data is used to detect and correct any errors in the previously programmed data before reprogramming the previously programmed data to different multi-level memory cells in the nonvolatile memory system.
摘要翻译：非易失性存储器系统包括主机系统，存储器控制器和包括多级闪存单元的闪存芯片。存储器控制器包括备用存储器，其适于在多级闪存单元的进一步编程失败时存储来自多级闪速存储器单元的先前编程的数据的备份副本。先前编程的数据的备份副本用于检测和纠正先前编程的数据中的任何错误，然后将先前编程的数据重新编程到非易失性存储器系统中的不同多级存储器单元。

6. 发明申请

US20060231835A1 Semiconductor device including ROM interface pad 审中-公开
标题翻译：半导体器件包括ROM接口板
公开(公告)号：US20060231835A1
公开(公告)日：2006-10-19
申请号：US11398313
申请日：2006-04-05
申请人： Jin-Hyeok Choi , Sam-Yong Bahng
发明人： Jin-Hyeok Choi , Sam-Yong Bahng
IPC分类号： H01L23/58
CPC分类号： H01L24/05 , H01L22/32 , H01L2224/02166 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/48091 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01082 , H01L2924/3011 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor device comprises a multilayer formed on a semiconductor substrate, the multilayer including a first circuit pattern, a second circuit pattern for testing the semiconductor device, the second circuit formed on a predetermined region of the multilayer, an inter-metal insulating layer formed on the second circuit pattern, a plurality of via contacts formed in the inter-metal insulating layer, and a plurality of ROM interface pads disposed on the inter-metal insulating layer, wherein the plurality of ROM interface pads are electrically connected with the second circuit pattern through the plurality of via contacts, and are separated from one another.
摘要翻译：半导体器件包括形成在半导体衬底上的多层，多层包括第一电路图案，用于测试半导体器件的第二电路图案，形成在多层的预定区域上的第二电路，形成在多层的预定区域上的金属间绝缘层所述第二电路图案，形成在所述金属间绝缘层中的多个通孔接头以及设置在所述金属间绝缘层上的多个ROM接口焊盘，其中所述多个ROM接口焊盘与所述第二电路图形电连接通过多个通孔触点，并且彼此分离。

7. 发明申请

US20050202855A1 Circuit and method for preserving data in sleep mode of semiconductor device using test scan chain 有权
标题翻译：使用测试扫描链在半导体器件的睡眠模式下保存数据的电路和方法
公开(公告)号：US20050202855A1
公开(公告)日：2005-09-15
申请号：US11061903
申请日：2005-02-18
申请人： Jin-Hyeok Choi , Sam-Yong Bahng
发明人： Jin-Hyeok Choi , Sam-Yong Bahng
IPC分类号： G11C11/40 , H04B1/06 , H04B1/16 , H04B7/00
CPC分类号： G11C29/32
摘要： A data storage circuit and a data preservation method for preserving data when a semiconductor device is in a sleep mode using a test scan chain are provided, where the data storage circuit includes a sleep mode control unit and a scan chain unit, the sleep mode control unit outputs a scan control signal and a scan clock signal in response to one of a test control signal and a sleep mode control signal received from the outside, stores an output data signal in a memory when the output data signal is received, and outputs a test pattern data signal as a scan data signal when the test pattern data signal is received, the scan chain unit outputs a normal data signal stored inside of the scan chain unit as the output data signal to the sleep mode control unit or receives and outputs the scan data signal to a combinational circuit unit in response to the scan control signal and the scan clock signal, and the data storage circuit and the data preservation method prevent a loss of data in a sleep mode of a semiconductor device, and reduce power consumption in a standby state.
摘要翻译：数据存储电路和数据保存方法，用于在半导体器件使用测试扫描链处于睡眠模式时保存数据，其中数据存储电路包括睡眠模式控制单元和扫描链单元，睡眠模式控制响应于从外部接收的测试控制信号和睡眠模式控制信号中的一个输出扫描控制信号和扫描时钟信号，当接收到输出数据信号时，将输出数据信号存储在存储器中，并输出测试图形数据信号作为扫描数据信号，当接收到测试图形数据信号时，扫描链单元将存储在扫描链单元内的正常数据信号作为输出数据信号输出到睡眠模式控制单元，或者接收并输出根据扫描控制信号和扫描时钟信号将数据信号扫描到组合电路单元，数据存储电路和数据保存方法防止数据丢失为半通道模式，并且在待机状态下降低功耗。

8. 发明授权

US06436755B1 Dynamic random access memory cell and method for fabricating the same 有权
标题翻译：动态随机存取存储单元及其制造方法
公开(公告)号：US06436755B1
公开(公告)日：2002-08-20
申请号：US09612850
申请日：2000-07-10
申请人： Jin Hyeok Choi
发明人： Jin Hyeok Choi
IPC分类号： H01L8242
CPC分类号： H01L27/108
摘要： A dynamic random access memory(DRAM) cell having no capacitor, comprising: a silicon layer doped with impurities of a first conductivity type; a metal oxide semiconductor (MOS) transistor having a gate formed on one surface of the silicon layer and a source and drain regions formed in the silicon layer, the source and the drain regions being doped with impurities of a second conductivity type to induce channel the silicon layer under the gate; an insulating layer formed on another surface of the silicon layer; a conduction layer for a plate electrode formed on the insulating layer; and a purge region formed in the silicon layer to purge minor carriers induced in an interface surface between the silicon layer and the insulating layer, the purge region doped with impurities of the first conductivity type.
摘要翻译：一种没有电容器的动态随机存取存储器（DRAM）单元，包括：掺杂有第一导电类型的杂质的硅层; 金属氧化物半导体（MOS）晶体管，其具有形成在硅层的一个表面上的栅极和形成在硅层中的源极和漏极区域，源极和漏极区域掺杂有第二导电类型的杂质以引发通道门下硅层; 形成在所述硅层的另一表面上的绝缘层; 形成在所述绝缘层上的用于平板电极的导电层; 以及形成在所述硅层中以清除在所述硅层和所述绝缘层之间的界面表面中感应的次要载流子的净化区域，所述净化区域掺杂有所述第一导电类型的杂质。

9. 发明申请

US20140082405A1 EMBEDDED MULTIMEDIA CARD (eMMC), HOST CONTROLLING eMMC, AND METHOD OPERATING eMMC SYSTEM 有权
标题翻译：嵌入式多媒体卡（eMMC），主机控制eMMC和操作eMMC系统的方法
公开(公告)号：US20140082405A1
公开(公告)日：2014-03-20
申请号：US14025879
申请日：2013-09-13
申请人： JUNG PIL LEE , JIN HYEOK CHOI , HWA SEOK OH , YOUNG-GYU KANG , SUNG HO SEO , MYUNG SUB SHIN , KYUNG PHIL YOO
发明人： JUNG PIL LEE , JIN HYEOK CHOI , HWA SEOK OH , YOUNG-GYU KANG , SUNG HO SEO , MYUNG SUB SHIN , KYUNG PHIL YOO
IPC分类号： G06F1/04
CPC分类号： G06F1/08 , G06F1/04 , G06F1/06 , G11C7/222
摘要： An embedded multimedia card (eMMC) includes a clock channel that receives a clock signal from a host, a command channel that receives a command from the host, a plurality of data channels that transmit data to the host, and a return clock channel that transmits a return clock synchronized with the data to the host.
摘要翻译：嵌入式多媒体卡（eMMC）包括从主机接收时钟信号的时钟信道，从主机接收命令的命令信道，向主机发送数据的多个数据信道以及发送数据的返回时钟信道与数据同步的返回时钟到主机。

10. 发明授权

US08230303B2 Memory system and data processing method thereof 有权
标题翻译：存储系统及其数据处理方法
公开(公告)号：US08230303B2
公开(公告)日：2012-07-24
申请号：US12512097
申请日：2009-07-30
申请人： Jin-Hyeok Choi , Hwaseok Oh , Jong-uk Song
发明人： Jin-Hyeok Choi , Hwaseok Oh , Jong-uk Song
IPC分类号： G11C29/00
CPC分类号： G11C16/26 , G06F11/1068 , G11C11/5628 , G11C11/5642 , G11C29/00 , G11C2211/5646
摘要： A data processing method of a memory system including a flash memory, which includes judging whether data initially read from a selected page of the flash memory is correctable. If the initially read data is judged not to be correctable, the data is newly read from the selected page based upon each of newly determined read voltages. Thereafter, error-free sub-sectors of the newly read data are collected based upon EDC data corresponding to the initially read data. The data of the error-free sub-sectors are then corrected based upon ECC data corresponding to the initially read data.
摘要翻译：一种包括闪速存储器的存储器系统的数据处理方法，其包括判断从闪速存储器的选定页面开始读取的数据是否可校正。如果初始读取的数据被判定为不可校正，则基于每个新确定的读取电压从所选择的页面重新读取数据。此后，基于与初始读取的数据相对应的EDC数据来收集新读取的数据的无差错子扇区。然后，基于与初始读取的数据相对应的ECC数据来校正无差错子扇区的数据。

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