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1. 发明授权

US08527925B2 Estimating clock skew 失效
标题翻译：估计时钟偏差
公开(公告)号：US08527925B2
公开(公告)日：2013-09-03
申请号：US13463857
申请日：2012-05-04
申请人： Hong Wei Dai , Gong Qiong Li , Jia Niu , Jun Tan
发明人： Hong Wei Dai , Gong Qiong Li , Jia Niu , Jun Tan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62 , G06F2217/84
摘要： The present invention relates to a method and an apparatus for estimating a clock skew. The method comprises: obtaining a basic clock skew of each clock tree in the circuit; judging whether two units are in a same clock domain; if they are in different clock domains, estimating the clock skew between units to be a larger one of basic clock skews of the clock trees corresponding to these two unit; if these two units are in the same clock domain, further judging whether they are in a same hierarchical logic block; if they are in different hierarchical logic blocks, estimating the clock skew between units to be the basic clock skew of the clock tree of these two units plus additional clock skew caused by different hierarchical logic blocks. The apparatus is corresponding to the method. With the method and apparatus, the clock skew in the circuit can be estimated more accurately, which improves the efficiency of circuit design.
摘要翻译：本发明涉及一种用于估计时钟偏差的方法和装置。该方法包括：获得电路中每个时钟树的基本时钟偏差; 判断两个单元是否处于相同的时钟域; 如果它们在不同的时钟域中，则将单元之间的时钟偏差估计为对应于这两个单元的时钟树的基本时钟偏差中较大的一个; 如果这两个单元在相同的时钟域中，则进一步判断它们是否处于相同的分层逻辑块中; 如果它们处于不同的分层逻辑块中，则估计单元之间的时钟偏差将成为这两个单元的时钟树的基本时钟偏差，以及由不同分层逻辑块引起的附加时钟偏移。该装置对应于该方法。利用该方法和装置，可以更精确地估计电路中的时钟偏移，这提高了电路设计的效率。

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