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1. 发明授权

US08386974B2 Accelerating coverage convergence using symbolic properties 有权
标题翻译：使用符号属性加速覆盖收敛
公开(公告)号：US08386974B2
公开(公告)日：2013-02-26
申请号：US13087304
申请日：2011-04-14
申请人： Parijat Biswas , Raghurama Krishna Srigiriraju , Alexandru Seibulescu , Jayant Nagda
发明人： Parijat Biswas , Raghurama Krishna Srigiriraju , Alexandru Seibulescu , Jayant Nagda
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In a method for increasing coverage convergence during verification of a design for an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Exemplary hardware code can include the hardware description language (HDL) code and/or the hardware verification language (HVL) code. Symbolic properties, which are derived from propagating the symbolic variables and symbolic expressions through the design and the test bench during the multiple simulation runs, can be collected. Coverage information from the multiple simulation runs can be analyzed to identify coverage points to be targeted. At this point, for each identified coverage point, the constraints resulting from the collected symbolic properties can be solved to generate directed stimuli for the design. These directed stimuli can increase the coverage convergence.
摘要翻译：在用于在集成电路的设计验证期间增加覆盖收敛的方法中，可以执行多个模拟运行。可以为设计的硬件代码和测试台中的变量和变量表达式生成符号变量和符号表达式。示例性硬件代码可以包括硬件描述语言（HDL）代码和/或硬件验证语言（HVL）代码。可以收集在多次模拟运行期间通过设计和测试台传播符号变量和符号表达式导出的符号属性。可以分析来自多个模拟运行的覆盖信息，以确定要定位的覆盖点。在这一点上，对于每个识别的覆盖点，可以解决从所收集的符号属性产生的约束，以产生用于设计的定向刺激。这些定向刺激可以增加覆盖收敛。

2. 发明申请

US20120266118A1 Accelerating Coverage Convergence Using Symbolic Properties 有权
标题翻译：使用符号属性加速覆盖收敛
公开(公告)号：US20120266118A1
公开(公告)日：2012-10-18
申请号：US13087304
申请日：2011-04-14
申请人： Parijat Biswas , Raghurama Krishna Srigiriraju , Alexandru Seibulescu , Jayant Nagda
发明人： Parijat Biswas , Raghurama Krishna Srigiriraju , Alexandru Seibulescu , Jayant Nagda
IPC分类号： G06F9/455
CPC分类号： G06F17/504
摘要： In a method for increasing coverage convergence during verification of a design for an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Exemplary hardware code can include the hardware description language (HDL) code and/or the hardware verification language (HVL) code. Symbolic properties, which are derived from propagating the symbolic variables and symbolic expressions through the design and the test bench during the multiple simulation runs, can be collected. Coverage information from the multiple simulation runs can be analyzed to identify coverage points to be targeted. At this point, for each identified coverage point, the constraints resulting from the collected symbolic properties can be solved to generate directed stimuli for the design. These directed stimuli can increase the coverage convergence.
摘要翻译：在用于在集成电路的设计验证期间增加覆盖收敛的方法中，可以执行多个模拟运行。可以为设计的硬件代码和测试台中的变量和变量表达式生成符号变量和符号表达式。示例性硬件代码可以包括硬件描述语言（HDL）代码和/或硬件验证语言（HVL）代码。可以收集在多次模拟运行期间通过设计和测试台传播符号变量和符号表达式导出的符号属性。可以分析来自多个模拟运行的覆盖信息，以确定要定位的覆盖点。在这一点上，对于每个识别的覆盖点，可以解决从所收集的符号属性产生的约束，以产生用于设计的定向刺激。这些定向刺激可以增加覆盖收敛。

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