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1. 发明授权

US07977248B2 Double patterning with single hard mask 有权
标题翻译：双重图案化与单个硬掩模
公开(公告)号：US07977248B2
公开(公告)日：2011-07-12
申请号：US12006204
申请日：2007-12-31
申请人： Elliot Tan , Michael K. Harper , James Jeong
发明人： Elliot Tan , Michael K. Harper , James Jeong
IPC分类号： H01L21/302
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to create a first plurality of fins in alignment with the first plurality of lines and the first resist layer is removed. A second resist layer is patterned on the hard mask as a second plurality of lines separated by a second defined pitch. The second plurality of lines is patterned between the first plurality of lines. The hard mask is etched to the portion of the formed thickness to create a second plurality of fins in alignment with the second plurality of lines. The first plurality of hard mask fins and the second plurality of hard mask fins are interwoven and have same thickness.
摘要翻译：通常，一方面，一种方法包括在半导体衬底上形成硬掩模。第一抗蚀剂层在硬掩模上被图案化为由第一限定间距分开的第一多个线。将硬掩模蚀刻成成形厚度的一部分以产生与第一多条线对准的第一多个翅片，并且去除第一抗蚀剂层。第二抗蚀剂层在硬掩模上被图案化为由第二限定间距分开的第二多个线。在第一组多行之间构图第二组线。将硬掩模蚀刻到所形成的厚度的部分以形成与第二多条线对准的第二多个翅片。第一多个硬掩模翅片和第二多个硬掩模翅片交织并具有相同的厚度。

2. 发明申请

US20090170316A1 Double patterning with single hard mask 有权
标题翻译：双重图案化与单个硬掩模
公开(公告)号：US20090170316A1
公开(公告)日：2009-07-02
申请号：US12006204
申请日：2007-12-31
申请人： Elliot Tan , Michael K. Harper , James Jeong
发明人： Elliot Tan , Michael K. Harper , James Jeong
IPC分类号： H01L21/308
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to create a first plurality of fins in alignment with the first plurality of lines and the first resist layer is removed. A second resist layer is patterned on the hard mask as a second plurality of lines separated by a second defined pitch. The second plurality of lines is patterned between the first plurality of lines. The hard mask is etched to the portion of the formed thickness to create a second plurality of fins in alignment with the second plurality of lines. The first plurality of hard mask fins and the second plurality of hard mask fins are interwoven and have same thickness.
摘要翻译：通常，一方面，一种方法包括在半导体衬底上形成硬掩模。第一抗蚀剂层在硬掩模上被图案化为由第一限定间距分开的第一多个线。将硬掩模蚀刻成成形厚度的一部分以产生与第一多条线对准的第一多个翅片，并且去除第一抗蚀剂层。第二抗蚀剂层在硬掩模上被图案化为由第二限定间距分开的第二多个线。在第一组多行之间构图第二组线。将硬掩模蚀刻到所形成的厚度的部分以形成与第二多条线对准的第二多个翅片。第一多个硬掩模翅片和第二多个硬掩模翅片交织并具有相同的厚度。

3. 发明申请

US20060000796A1 Method for controlling critical dimensions and etch bias 审中-公开
标题翻译：控制临界尺寸和蚀刻偏压的方法
公开(公告)号：US20060000796A1
公开(公告)日：2006-01-05
申请号：US10882982
申请日：2004-06-30
申请人： Elliot Tan , James Jeong , Qiang Fu
发明人： Elliot Tan , James Jeong , Qiang Fu
IPC分类号： B44C1/22 , H01L21/302
CPC分类号： H01L21/31144 , H01L21/31116
摘要： In one embodiment a method is provided. The method, comprises performing at least one deposition operation to laminate portions of a patterned photoresist that experiences degradation when bombarded with an etchant plasma during a subsequent plasma etching operation and performing the plasma etching operation.
摘要翻译：在一个实施例中提供了一种方法。该方法包括执行至少一个沉积操作，以在随后的等离子体蚀刻操作期间用蚀刻剂等离子体轰击时，经历降解的图案化光致抗蚀剂的部分，并执行等离子体蚀刻操作。

4. 发明申请

US20090124084A1 FABRICATION OF SUB-RESOLUTION FEATURES FOR AN INTEGRATED CIRCUIT 审中-公开
标题翻译：一体化电路分解特性的制作
公开(公告)号：US20090124084A1
公开(公告)日：2009-05-14
申请号：US11940121
申请日：2007-11-14
申请人： Elliot Tan , James Jeong
发明人： Elliot Tan , James Jeong
IPC分类号： H01L21/467
CPC分类号： H01L21/76816
摘要： A method for fabricating sub-resolution features on an integrated circuit comprises depositing a hard mask layer on a dielectric layer of a semiconductor substrate, patterning the hard mask layer to form hard mask structures that define trenches, etching trenches in the dielectric layer through the hard mask structures, thereby forming a first set of dielectric structures on the substrate, depositing a conformal layer on the substrate and the first set of dielectric structures, etching the conformal layer to form spacers adjacent to the first set of dielectric structures, depositing a second dielectric layer within the trenches, thereby forming a second set of dielectric structures on the substrate, and etching the spacers to form sub-resolution trenches between the dielectric structures of the first and second set.
摘要翻译：一种用于在集成电路上制造子分辨率特征的方法包括在半导体衬底的电介质层上沉积硬掩模层，图案化硬掩模层以形成限定沟槽的硬掩模结构，通过硬的蚀刻电介质层中的沟槽掩模结构，从而在衬底上形成第一组介电结构，在衬底和第一组电介质结构上沉积共形层，蚀刻保形层以形成邻近第一组电介质结构的间隔物，沉积第二电介质层，从而在衬底上形成第二组电介质结构，并蚀刻间隔物以在第一和第二组的电介质结构之间形成次分辨率沟槽。

5. 发明授权

US07112534B2 Process for low k dielectric plasma etching with high selectivity to deep uv photoresist 失效
标题翻译：用于低k电介质等离子体蚀刻的工艺，具有对深紫外光致抗蚀剂的高选择性
公开(公告)号：US07112534B2
公开(公告)日：2006-09-26
申请号：US10672357
申请日：2003-09-25
申请人： Qiang Fu , James Jeong
发明人： Qiang Fu , James Jeong
IPC分类号： H01L21/302
CPC分类号： H01L21/31138
摘要： A method of forming a microelectronic structure and its associated structures is described. That method comprises forming and patterning a deep uv resist layer on a substrate, etching the substrate in a plasma generated from a gas comprising a carbon to fluorine ratio from about 1:1 to about 2:3 to form substantially vertical sidewalls in the deep uv resist layer.
摘要翻译：描述了形成微电子结构及其相关结构的方法。该方法包括在衬底上形成和图案化深紫外光阻层，在从包含碳比至大约1:1-约2:3的碳与氟的气体产生的等离子体中蚀刻衬底，以在深紫外抗蚀剂层。

6. 发明申请

US20050070116A1 Process for low k dielectric plasma etching with high selectivity to deep uv photoresist 失效
标题翻译：用于低k电介质等离子体蚀刻的工艺，具有对深紫外光致抗蚀剂的高选择性
公开(公告)号：US20050070116A1
公开(公告)日：2005-03-31
申请号：US10672357
申请日：2003-09-25
申请人： Qiang Fu , James Jeong
发明人： Qiang Fu , James Jeong
IPC分类号： H01L21/311 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31138
摘要： A method of forming a microelectronic structure and its associated structures is described. That method comprises forming and patterning a deep uv resist layer on a substrate, etching the substrate in a plasma generated from a gas comprising a carbon to fluorine ratio from about 1:1 to about 2:3 to form substantially vertical sidewalls in the deep uv resist layer.
摘要翻译：描述了形成微电子结构及其相关结构的方法。该方法包括在衬底上形成和图案化深紫外光阻层，在从包含碳比至大约1:1-约2:3的碳与氟的气体产生的等离子体中蚀刻衬底，以在深紫外抗蚀剂层。

7. 发明申请

US20060057852A1 Process for low k dielectric plasma etching with high selectivity to deep uv photoresist 审中-公开
公开(公告)号：US20060057852A1
公开(公告)日：2006-03-16
申请号：US11271408
申请日：2005-11-09
申请人： Qiang Fu , James Jeong
发明人： Qiang Fu , James Jeong
IPC分类号： H01L21/311
CPC分类号： H01L21/31138
摘要： A method of forming a microelectronic structure and its associated structures is described. That method comprises forming and patterning a deep uv resist layer on a substrate, etching the substrate in a plasma generated from a gas comprising a carbon to fluorine ratio from about 1:1 to about 2:3 to form substantially vertical sidewalls in the deep uv resist layer.

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