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1. 发明申请

US20100118195A1 REMOTE CONTROL DEVICE AND OPERATING METHOD THEREOF, AND IMAGE DISPLAY APPARATUS CONTROLLED BY REMOTE CONTROL DEVICE 审中-公开
标题翻译：远程控制装置及其操作方法以及远程控制装置控制的图像显示装置
公开(公告)号：US20100118195A1
公开(公告)日：2010-05-13
申请号：US12606350
申请日：2009-10-27
申请人： Ju-il EOM , Jae-uk HAN , Jong-ho LEE , Jin-sun PARK , Seok-jae RHEE
发明人： Ju-il EOM , Jae-uk HAN , Jong-ho LEE , Jin-sun PARK , Seok-jae RHEE
IPC分类号： H04N5/445 , H04N5/44 , G06F3/033
CPC分类号： H04N5/4403 , A63F13/00 , G08C17/00 , G08C2201/30 , H04N5/44513 , H04N5/44591 , H04N5/45 , H04N21/42206 , H04N21/42222 , H04N21/4316 , H04N2005/4428 , H04N2005/4432 , H04N2005/4442
摘要： A remote control device capable of being separated into two or more parts is provided. The remote control device includes a first remote controller, and a second remote controller which is capable of being connected to or separated from the first remote controller. If the first remote controller and the second remote controller are connected, the first remote controller and the second remote controller may function as a single unit, or if not, the first remote controller and the second remote controller may function as individual units.
摘要翻译：提供能够分离成两个或多个部件的遥控装置。遥控装置包括第一遥控器和能够连接到第一遥控器或与第一遥控器分离的第二遥控器。如果连接了第一遥控器和第二遥控器，则第一遥控器和第二遥控器可以用作单个单元，或者如果不是，则第一遥控器和第二遥控器可以用作单独的单元。

2. 发明授权

US07554869B2 Semiconductor memory device having internal circuits responsive to temperature data and method thereof 失效
标题翻译：具有响应于温度数据的内部电路的半导体存储器件及其方法
公开(公告)号：US07554869B2
公开(公告)日：2009-06-30
申请号：US10981652
申请日：2004-11-05
申请人： Soo-Young Kim , Sang-Jae Rhee , Min-Gyu Hwang
发明人： Soo-Young Kim , Sang-Jae Rhee , Min-Gyu Hwang
IPC分类号： G11C7/04
CPC分类号： G11C7/06 , G11C5/147 , G11C7/04 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , H03K3/012 , H03K17/164 , H03K2217/0036
摘要： A semiconductor memory device having internal circuits responsive to temperature data, in order to compensate an output characteristic change of the internal circuits and reduce power consumption depending on temperature change, and method thereof are disclosed. The semiconductor memory device may include a temperature sensing circuit and an internal circuit. The temperature sensing circuit may generate and output temperature data in response to ambient temperature of the semiconductor memory device. The internal circuit may adjust an output level of an output signal in response to the temperature data from the temperature sensing circuit.
摘要翻译：具有响应于温度数据的内部电路的半导体存储器件及其方法被公开，以便补偿内部电路的输出特性变化并降低根据温度变化的功耗。半导体存储器件可以包括温度检测电路和内部电路。温度检测电路可以响应于半导体存储器件的环境温度产生和输出温度数据。内部电路可以响应于来自温度感测电路的温度数据来调节输出信号的输出电平。

3. 发明申请

US20070155798A1 Novel oxazolidinone derivatives 有权
标题翻译：新型恶唑烷酮衍生物
公开(公告)号：US20070155798A1
公开(公告)日：2007-07-05
申请号：US10596412
申请日：2004-12-17
申请人： Jae Rhee , Weon Im , Chong Cho , Sung Choi , Tae Lee
发明人： Jae Rhee , Weon Im , Chong Cho , Sung Choi , Tae Lee
IPC分类号： A61K31/4439 , C07D413/14
CPC分类号： A61K31/4439 , A61K31/675 , C07D263/32 , C07D413/14 , C07D417/10 , C07D417/14 , C07F9/653 , C07F9/65583
摘要： The present invention relates to novel derivatives of oxazolidinone, a method thereof and pharmaceutical compositions comprising the derivatives for use in an antibiotic. The oxazolidinone derivatives of the present invention show inhibitory activity against a broad spectrum of bacteria and lower toxicity. The prodrugs, prepared by reacting the compound having hydroxyl group with amino acid or phosphate, have an excellent efficiency on solubility thereof against water. Further, the derivatives of the present invention may exert potent antibacterial activity versus various human and animal pathogens, including Gram-positive bacteria such as Staphylococi, Enterococci and Streptococi, anaerobic microorganisms such as Bacteroides and Clostridia, and acid-resistant microorganisms such as Mycobacterium tuberculosis and Mycobacterium avium. Accordingly, the compositions comprising the oxazolidinone are used in an antibiotic. Data supplied from the esp@cenet database—Worldwide
摘要翻译：本发明涉及恶唑烷酮的新衍生物，其方法和药物组合物，其包含用于抗生素的衍生物。本发明的恶唑烷酮衍生物显示出对广谱细菌的抑制活性和较低的毒性。通过使具有羟基的化合物与氨基酸或磷酸酯反应制备的前药在对水的溶解性方面具有优异的效果。此外，本发明的衍生物可以相对于各种人和动物病原体，包括葡萄球菌，肠球菌和链球菌等革兰阳性菌，拟杆菌和梭菌等厌氧菌，耐结核菌如结核分枝杆菌和鸟分枝杆菌。因此，包含恶唑烷酮的组合物用于抗生素中。从esp @ cenet database-Worldwide提供的数据

4. 发明申请

US20060016416A1 Polymeric manifold assembly and method 审中-公开
标题翻译：聚合歧管总成及方法
公开(公告)号：US20060016416A1
公开(公告)日：2006-01-26
申请号：US11156327
申请日：2005-06-17
申请人： Dukhyung Kim , Timothy Keighron , Jae Rhee , Randy Stull
发明人： Dukhyung Kim , Timothy Keighron , Jae Rhee , Randy Stull
IPC分类号： F02M35/10
CPC分类号： F02M35/10347 , F02M35/10072 , F02M35/10321 , F02M35/1036 , F02M35/1045 , F02M35/116
摘要： A method for manufacturing an engine intake manifold assembly is provided. The method includes forming a top, middle, and bottom section of the manifold assembly in an injection molding process, each including cavities defined with positive draft angles, the cavities defining a plurality of internal passageways in an assembled state of the manifold assembly. The top, middle, and bottom sections are joined to form the manifold assembly through vibration welding or ultrasonic welding. An engine intake manifold assembly having top, middle, and bottom sections joined through vibration welding or ultrasonic welding is also provided.
摘要翻译：提供一种制造发动机进气歧管组件的方法。该方法包括在注射模制过程中形成歧管组件的顶部，中部和底部部分，每个包括限定有正拔模斜角的空腔，空腔在歧管组件的组装状态下限定多个内部通道。顶部，中部和底部通过振动焊接或超声波焊接连接形成歧管组件。还提供了通过振动焊接或超声波焊接连接的顶部，中部和底部的发动机进气歧管组件。

5. 发明授权

US06930948B2 Semiconductor memory device having an internal voltage generation circuit for selectively generating an internal voltage according to an external voltage level 失效
标题翻译：具有内部电压产生电路的半导体存储器件，用于根据外部电压电平选择性地产生内部电压
公开(公告)号：US06930948B2
公开(公告)日：2005-08-16
申请号：US10621165
申请日：2003-07-15
申请人： Kyu-Chan Lee , Sang-Jae Rhee , Jung-Yong Choi , Jong-Hyun Choi , Jong-Sik Na , Jae-Hoon Kim
发明人： Kyu-Chan Lee , Sang-Jae Rhee , Jung-Yong Choi , Jong-Hyun Choi , Jong-Sik Na , Jae-Hoon Kim
IPC分类号： G11C5/14 , G11C11/00
CPC分类号： G11C5/147
摘要： An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.
摘要翻译：外部高/低电压兼容半导体存储器件包括内部电压焊盘，内部电压产生电路和内部电压控制信号产生电路。内部电压焊盘将低外部电压与内部电压连接，并且内部电压产生电路响应于内部电压控制信号和高外部电压而产生内部电压。内部电压控制信号发生电路根据高或低的外部电压产生内部电压控制信号。因此，由于内部电压控制信号，可以管理半导体存储器件的数据库，而不将数据库分类为用于低电压的高电压数据库和数据库。此外，内部电压电平稳定，因为根据外部电压的电压电平调节提供给内部电压的电荷。

6. 发明授权

US06370068B2 Semiconductor memory devices and methods for sampling data therefrom based on a relative position of a memory cell array section containing the data 有权
标题翻译：半导体存储器件和方法，用于根据包含数据的存储单元阵列部分的相对位置对其数据进行采样
公开(公告)号：US06370068B2
公开(公告)日：2002-04-09
申请号：US09755977
申请日：2001-01-05
申请人： Sang-Jae Rhee
发明人： Sang-Jae Rhee
IPC分类号： G11C722
CPC分类号： G11C7/1057 , G11C7/1006 , G11C7/1012 , G11C7/1051
摘要： Semiconductor devices and methods of sampling data therefrom are provided in which data is sampled from a memory cell array based on a relative position of a memory cell array section that contains the data. A sense amplifier generates an output signal in response to an address of one or more cells in a memory cell array. A control circuit generates a sample control signal in response to at least a portion of the address (e.g., one or more high order bits of the address) of the one or more cells in the memory cell array. A data sampling circuit then samples the output signal of the sense amplifier in response to the sample control signal. The portion of the memory cell array address used to drive the control circuit may logically divide the memory cell array into two or more sections. The control circuit may adjust the timing of the sample control signal in accordance with the proximity of a memory cell array section to the sense amplifier.
摘要翻译：提供半导体器件及其数据采样方法，其中基于包含数据的存储单元阵列部分的相对位置从存储器单元阵列采样数据。感测放大器响应于存储器单元阵列中的一个或多个单元的地址产生输出信号。控制电路响应于存储器单元阵列中的一个或多个单元的地址的至少一部分（例如，地址的一个或多个高位）而产生采样控制信号。然后，数据采样电路响应于采样控制信号对读出放大器的输出信号进行采样。用于驱动控制电路的存储单元阵列地址的部分可逻辑地将存储单元阵列划分成两个或多个区段。控制电路可以根据存储单元阵列部分与感测放大器的接近度来调整采样控制信号的定时。

7. 发明授权

US06362656B1 Integrated circuit memory devices having programmable output driver circuits therein 有权
公开(公告)号：US06362656B1
公开(公告)日：2002-03-26
申请号：US09753927
申请日：2001-01-03
申请人： Sang-jae Rhee
发明人： Sang-jae Rhee
IPC分类号： H03K190175
摘要： Output drivers preferably contain a plurality of driver circuits therein that are commonly connected to an output line to be driven and can be selectively enabled or disabled to increase or decrease drive capability, respectively. Driver circuits may include first and second control signal lines (e.g., MRS1, MRS2), a first pull-up/pull-down driver circuit having first and second data inputs, a first control input electrically coupled to the first control signal line (e.g., MRS1) and a second control input, and a second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to the second control signal line (e.g., MRS2) and a second control input. First and second complementary control signals lines (e.g., {overscore (MRS1+L )}, {overscore (MRS2+L )}) are also preferably provided and the second control inputs of the first pull-up/pull-down driver circuit and second pull-up/pull-down driver circuit are electrically coupled to the first and second complementary control signal lines, respectively. These control signal lines and complementary control signal lines can be used to control the number of driver circuits that are active within the output driver, based on loading conditions.

8. 发明授权

US06314029B1 Memory device having I/O sense amplifier with variable current gain 有权
标题翻译：具有可变电流增益的I / O读出放大器的存储器件
公开(公告)号：US06314029B1
公开(公告)日：2001-11-06
申请号：US09543677
申请日：2000-04-07
申请人： Tae-Young Ko , Sang-jae Rhee
发明人： Tae-Young Ko , Sang-jae Rhee
IPC分类号： G11C708
CPC分类号： G11C7/06 , G11C8/12
摘要： A semiconductor memory device having input/output sense amplifiers capable of varying gains using a column address and block selection signals. The input/output sense amplifiers can compensate for reduction of transfer rate according to distance between a selected memory block or sub memory block and the sense amplifiers. A semiconductor memory device of the present invention includes: a plurality of sub memory blocks divided by a column address in a memory block; a plurality of data input/output line pairs coupled to the sub memory blocks, for transmitting data in a selected sub memory block; and a plurality of input/output sense amplifiers for sensing and amplifying data from the data input/output line pairs, wherein each of the input/output sense amplifiers has a variable gain characteristic depending on distance between the selected sub memory block and the input/output sense amplifiers so as to minimize a difference in delay characteristic according to position of the selected sub memory block.
摘要翻译：具有能够使用列地址和块选择信号来改变增益的输入/输出读出放大器的半导体存储器件。输入/输出读出放大器可根据所选存储块或子存储块与读出放大器之间的距离补偿传输速率的降低。本发明的半导体存储器件包括：多个子存储器块，被存储块中的列地址划分; 耦合到子存储器块的多个数据输入/输出线对，用于在所选择的子存储器块中发送数据; 以及用于感测和放大来自数据输入/输出线对的数据的多个输入/输出读出放大器，其中每个输入/输出读出放大器具有取决于所选择的子存储块与输入/输出线对之间的距离的可变增益特性，输出读出放大器，以便根据所选择的子存储块的位置最小化延迟特性的差异。

9. 发明授权

US5946242A Internal source voltage generator for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的内部源电压发生器
公开(公告)号：US5946242A
公开(公告)日：1999-08-31
申请号：US883537
申请日：1997-06-26
申请人： Soo-In Cho , Sang-Jae Rhee
发明人： Soo-In Cho , Sang-Jae Rhee
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C29/06 , G11C29/50 , G11C7/00
CPC分类号： G11C5/147 , G11C29/50 , G11C11/401
摘要： A circuit for generating an internal source voltage signal responsive to an external source voltage signal in a semiconductor memory device prevents malfunction and extends the lifetime of the device by clamping the internal source signal if the device is in a normal operating mode when the external source signal is in a stress operating range. When the device is placed in a test mode, the circuit allows the internal source signal to increase in proportion to the level of the external source signal when the external source signal is in a stress operating range. The circuit includes in internal source voltage generator, which always clamps the internal source signal when the external source signal is in a normal operating range, and a pull-up unit which is activated in response to a control signal. The control signal is enabled when the device is placed in a test mode by combining external timing signals.
摘要翻译：用于在半导体存储器件中产生响应于外部源极电压信号的内部源极电压信号的电路防止故障，并且如果器件处于正常工作模式时通过钳位内部源极信号来延长器件的寿命，当外部源极信号处于压力操作范围。当器件处于测试模式时，当外部源极信号处于应力工作范围时，该电路允许内部源极信号与外部源极信号的电平成正比。该电路包括内部源电压发生器，当外部源极信号处于正常工作范围时，它始终夹紧内部源极信号，以及响应控制信号激活的上拉单元。当通过组合外部定时信号将器件置于测试模式时，控制信号被使能。

10. 发明申请

US20080195919A1 SEMICONDUCTOR MEMORY DEVICE FOR BYTE-BASED MASKING OPERATION AND METHOD OF GENERATING PARITY DATA 有权
标题翻译：用于基于字节的屏蔽操作的半导体存储器件和产生奇偶性数据的方法
公开(公告)号：US20080195919A1
公开(公告)日：2008-08-14
申请号：US11865856
申请日：2007-10-02
申请人： Bok-gue Park , Uk-song Kang , Sang-jae Rhee
发明人： Bok-gue Park , Uk-song Kang , Sang-jae Rhee
IPC分类号： H03M13/03
CPC分类号： H03M13/19 , G06F11/1044 , H03M13/611
摘要： A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.
摘要翻译：半导体存储器件包括存储单元阵列和纠错码（ECC）引擎。存储单元阵列在其中存储正常数据和奇偶校验数据的位。 ECC引擎在掩蔽模式中执行掩蔽操作，ECC引擎使用正常数据来计算奇偶校验数据。正常数据包括要被更新的第一部分和将被掩蔽操作保存的第二部分。

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