会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Semiconductor device having low resistance values at connection points
of conductor layers
    • 在导体层的连接点具有低电阻值的半导体器件
    • US5500560A
    • 1996-03-19
    • US974719
    • 1992-11-12
    • Isao Kano
    • Isao Kano
    • H01L21/28H01L21/3205H01L21/768H01L23/52H01L23/522H01L23/532H01L23/48H01L29/40
    • H01L23/5226H01L23/53242H01L23/53247H01L2924/0002
    • In a semiconductor device having a first conductor layer (25) formed on a first insulator layer (23) and a second insulator layer (29) formed on the first conductor layer, a second conductor layer (31) has a primary conductor film (35) formed on the second insulator layer, a secondary conductor film (37) formed on the primary conductor film, and a ternary conductor film (63) formed on the secondary conductor film. The second insulator layer has a recessed surface (29b) which defines a contact perforation exposing a predetermined area of an upper surface (25a) of the first conductor layer. The secondary conductor film is further formed on the recessed surface and the predetermined area. The primary conductor film has a primary resistance value. The secondary conductor film has a secondary resistance value which is lower than the primary resistance value.
    • 在具有形成在第一绝缘体层(23)上的第一导体层(25)和形成在第一导体层上的第二绝缘体层(29)的半导体器件中,第二导体层(31)具有主导体膜 ),形成在第一绝缘体层上的次级导体膜(37)和形成在二次导体膜上的三元导体膜(63)。 第二绝缘体层具有限定暴露第一导体层的上表面(25a)的预定区域的接触穿孔的凹陷表面(29b)。 次级导体膜进一步形成在凹面和预定区域上。 主导体膜具有初级电阻值。 次级导体膜的次级电阻值低于初级电阻值。
    • 3. 发明授权
    • Process for forming a multilayer wiring conductor structure in
semiconductor device
    • 用于在半导体器件中形成多层布线导体结构的工艺
    • US5380679A
    • 1995-01-10
    • US130854
    • 1993-10-04
    • Isao Kano
    • Isao Kano
    • H01L21/3205H01L21/768H01L21/443
    • H01L21/76885Y10S438/948
    • In a process for forming a multilayer wiring conductor structure, an interlayer insulator film is deposited on a surface including an upper surface of a lower layer wiring conductor, and the deposited interlayer insulator film is planarized so as to expose the upper surface of the lower layer wiring conductor. Then, a bonding metal film is deposited on a surface of the interlayer insulator film exposing the upper surface of the lower layer wiring conductor, and a photoresist film is coated on the bonding metal film and patterned. By using the patterned photoresist, a hole for formation of a connection pillar between the lower layer wiring conductor and a possible upper layer wiring conductor and a patterning of the bonding metal film are simultaneously formed. Accordingly, the bonding metal film can be formed and patterned on the upper surface of the lower layer wiring conductor without increasing the photolithography steps.
    • 在用于形成多层布线导体结构的工艺中,在包括下层布线导体的上表面的表面上沉积层间绝缘膜,并且将沉积的层间绝缘膜平坦化以暴露下层的上表面 接线导体。 然后,在暴露下层布线导体的上表面的层间绝缘膜的表面上沉积粘合金属膜,并且将光致抗蚀剂膜涂覆在接合金属膜上并图案化。 通过使用图案化的光致抗蚀剂,同时形成用于在下层布线导体和可能的上层布线导体之间形成连接柱的孔和接合金属膜的图案化。 因此,可以在下层布线导体的上表面上形成和图案化接合金属膜,而不增加光刻步骤。
    • 8. 发明授权
    • Wafer having a plurality of IC chips having different sizes formed
thereon
    • 晶片具有形成在其上的具有不同尺寸的多个IC芯片
    • US5912502A
    • 1999-06-15
    • US41505
    • 1998-03-12
    • Isao Kano
    • Isao Kano
    • H01L27/04G01R31/28H01L21/822H01L21/02
    • G01R31/2884G01R31/2831
    • In a wafer having a plurality of integrated circuit chips of different chip sizes formed on the wafer, each of the integrated circuit chips having a number of externally connecting lands uniformly distributed over the whole surface of the chip with equal pitches to depict a matrix or a repeated pattern of an equilateral triangle, a plurality of power supply lands of the externally connecting lands are located to depict a cross having a crossing point positioned at a center of the chip. A geometrical location of the power supply lands is congruent to all said integrated circuit chips of different chip sizes. The pitch between adjacent lands positioning a dicing line therebetween is one obtained by multiplying the pitch between adjacent lands positioning no dicing line therebetween, by a positive integer.
    • 在具有形成在晶片上的多个不同芯片尺寸的集成电路芯片的晶片中,每个集成电路芯片具有多个外部连接的焊盘,其均匀地分布在芯片的整个表面上,以等间距来描绘矩阵或 等边三角形的重复图案,外部连接焊盘的多个电源焊盘被定位成描绘具有位于芯片中心的交叉点的十字。 电源焊盘的几何位置与所有不同芯片尺寸的所述集成电路芯片一致。 在它们之间定位切割线的相邻平台之间的间距是通过将其间没有切割线定位的相邻平台之间的间距乘以正整数而获得的。