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    • 3. 发明授权
    • Thin film transistor display panel and manufacturing method thereof
    • 薄膜晶体管显示面板及其制造方法
    • US08884291B2
    • 2014-11-11
    • US13172200
    • 2011-06-29
    • Su-Hyoung KangYoon Ho KhangDong Jo KimHyun Jae Na
    • Su-Hyoung KangYoon Ho KhangDong Jo KimHyun Jae Na
    • H01L29/04H01L29/786H01L29/417H01L29/45
    • H01L27/1248H01L23/291H01L23/3171H01L29/41733H01L29/45H01L29/78606H01L29/7869H01L2924/0002H01L2924/00
    • A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. The thin film transistor array panel includes: a gate electrode; a source electrode and a drain electrode spaced apart from each other, each of the source and drain electrodes comprising a lower layer and an upper layer; an insulating layer disposed between the gate electrode and the source and drain electrodes; a semiconductor, the source electrode and the drain electrode being electrically connected to the semiconductor; a first passivation layer contacting the lower layer of the source and drain electrodes but not contacting the upper layer of the source and drain electrodes; and a second passivation layer disposed on the upper layer of the source and drain electrodes. The first passivation layer may be made of silicon oxide, and the second passivation may be made of silicon nitride.
    • 一种薄膜晶体管阵列面板和能够形成由不同材料制成的绝缘层的制造方法,用于与氧化物半导体和第二部分接触的部分,而不需要额外的工艺。 薄膜晶体管阵列面板包括:栅电极; 源电极和漏电极彼此间隔开,源极和漏极中的每一个包括下层和上层; 绝缘层,设置在所述栅极电极和所述源极和漏极之间; 半导体,源电极和漏极电连接到半导体; 第一钝化层接触源极和漏极的下层,但不接触源极和漏极的上层; 以及设置在源电极和漏电极的上层上的第二钝化层。 第一钝化层可以由氧化硅制成,并且第二钝化可以由氮化硅制成。