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1. 发明申请

US20140075265A1 Outputting Information of ECC Corrected Bits 有权
标题翻译： ECC校正位的输出信息
公开(公告)号：US20140075265A1
公开(公告)日：2014-03-13
申请号：US13612433
申请日：2012-09-12
申请人： Chun-Hsiung Hung , Hsin Yi Ho
发明人： Chun-Hsiung Hung , Hsin Yi Ho
IPC分类号： H03M13/05
CPC分类号： G06F11/1084 , G06F11/1048 , G11C16/349 , G11C29/42 , G11C29/44 , G11C2029/0409 , G11C2029/0411
摘要： The present invention provides a method of operating a memory device storing error correcting codes ECCs for corresponding data and including ECC logic to correct errors using the ECCs. The method includes correcting data using ECCs for the data on the memory device, and producing information on the memory device about the use of the ECCs. The method provides the ECC information on an output port of the device in response to a command received on an input port from a process external to the memory device. The present invention also provides a method of controlling a memory device. The method includes sending a command to the memory device requesting ECC information corresponding to data in the memory device, and receiving the ECC information from the memory device in response to the command. The method includes performing a memory management function using the ECC information.
摘要翻译：本发明提供了一种操作存储装置的方法，该存储装置存储用于相应数据的纠错码ECC，并且包括ECC逻辑以使用ECC来校正错误。该方法包括使用用于存储器设备上的数据的ECC来校正数据，以及在存储器设备上产生关于使用ECC的信息。该方法响应于从存储设备外部的进程在输入端口上接收到的命令来向设备的输出端口提供ECC信息。本发明还提供一种控制存储器件的方法。该方法包括向存储器件发送请求与存储器件中的数据相对应的ECC信息的命令，以及响应该命令从存储器件接收ECC信息。该方法包括使用ECC信息执行存储器管理功能。

2. 发明授权

US08258815B2 Clock generator circuits for generating clock signals 有权
标题翻译：用于产生时钟信号的时钟发生器电路
公开(公告)号：US08258815B2
公开(公告)日：2012-09-04
申请号：US12716912
申请日：2010-03-03
申请人： Chia Ching Li , Hsin Yi Ho , Chun Hsiung Hung
发明人： Chia Ching Li , Hsin Yi Ho , Chun Hsiung Hung
IPC分类号： H03K19/096 , H03K5/01
CPC分类号： H03K19/096
摘要： The present invention relates to a circuit for generating a clock signal. The circuit comprises a current source to generate a reference current and provide a first voltage V1, a first current generator to generate a first mirror current during a first half cycle based on the reference current, a first capacitor including a first end, and a first transistor having a first threshold voltage VTH1. The first transistor includes a gate to receive the first voltage V1, a drain coupled to the first current generator and a source coupled to the first end of the first capacitor so as to allow the first mirror current to charge the first capacitor during the first half cycle, wherein the period of the first half cycle is a function of the first bias voltage V1 minus the first threshold voltage VTH1.
摘要翻译：本发明涉及一种用于产生时钟信号的电路。该电路包括用于产生参考电流并提供第一电压V1的电流源，第一电流发生器，用于在基于参考电流的第一半周期期间产生第一反射镜电流，第一电容器，包括第一端和第一电压晶体管具有第一阈值电压VTH1。第一晶体管包括接收第一电压V1的栅极，耦合到第一电流发生器的漏极和耦合到第一电容器的第一端的源，以便允许第一反射镜电流在第一半期间对第一电容器充电循环，其中所述前半周期的周期是所述第一偏置电压V1减去所述第一阈值电压VTH1的函数。

3. 发明授权

US07961513B2 Method for programming a multilevel memory 有权
标题翻译：多级存储器编程方法
公开(公告)号：US07961513B2
公开(公告)日：2011-06-14
申请号：US12544025
申请日：2009-08-19
申请人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
发明人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5671 , G11C2211/5621
摘要： A method for programming a MLC memory includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.
摘要翻译：用于编程MLC存储器的方法包括（a）通过使用Vd偏置BL将具有低于目标编程状态的PV电平的Vt电平的存储器的位编程为编程位; （b）如果存储器的每个位的Vt电平不低于目标编程状态的PV电平，则结束该方法，否则继续步骤（c）; 以及（c）设定BL = BL + K1，并且如果每个编程的比特都具有低于PV水平的Vt级别，而设置BL = BL-K2，并重复步骤（a），如果在至少一个编程位的Vt电平不低于PV电平。

4. 发明申请

US20110085378A1 Memory and Operation Method Therefor 有权
标题翻译：记忆及其操作方法
公开(公告)号：US20110085378A1
公开(公告)日：2011-04-14
申请号：US12576323
申请日：2009-10-09
申请人： Hsin-Yi Ho , Chun-Hsiung Hung , Yun-Chen Chou
发明人： Hsin-Yi Ho , Chun-Hsiung Hung , Yun-Chen Chou
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G11C16/26 , G11C16/349
摘要： In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage.
摘要翻译：在包括多个存储单元的存储器的操作方法中，通过施加参考电压对存储器单元执行第一读取; 如果检查到第一读取结果不正确，则移动参考电压; 通过施加移动的参考电压对存储器单元执行第二读取; 如果检查到第二读取结果不正确，则将第一读取中的第一逻辑状态的第一总数与第二读取中的第一逻辑状态的第二总数进行比较; 并且如果第一读取结果具有与第二读取结果相同数量的第一逻辑状态，并且移动的参考电压被存储为目标参考电压，则参考电压的移动停止。

5. 发明申请

US20110058414A1 MEMORY WITH MULTIPLE REFERENCE CELLS 有权
标题翻译：具有多个参考电池的存储器
公开(公告)号：US20110058414A1
公开(公告)日：2011-03-10
申请号：US12555872
申请日：2009-09-09
申请人： Hsin-Yi Ho , Chia-Ching Li
发明人： Hsin-Yi Ho , Chia-Ching Li
IPC分类号： G11C16/04 , G11C16/06 , G11C7/02
CPC分类号： G11C7/04 , G11C11/56 , G11C11/5642 , G11C2211/5634
摘要： A memory includes a memory array, a sense amplifier, and a reference circuit. The memory array includes a memory cell. The sense amplifier includes a first terminal coupled to the memory cell and a second terminal. The reference circuit includes a first reference cell, a second reference cell, and a switch. The first reference cell has a first reference threshold voltage for providing a first reference current, based on a first reference word line voltage. The second reference cell has a second reference threshold voltage for providing a second reference current, based on a second reference word line voltage. The switch selectively provides one of the first and the second reference currents to the second terminal in response to a control signal. The first and the second reference word line voltages correspond to different voltage levels.
摘要翻译：存储器包括存储器阵列，读出放大器和参考电路。存储器阵列包括存储器单元。读出放大器包括耦合到存储单元的第一端子和第二端子。参考电路包括第一参考单元，第二参考单元和开关。第一参考单元具有用于基于第一参考字线电压提供第一参考电流的第一参考阈值电压。第二参考单元具有第二参考阈值电压，用于基于第二参考字线电压提供第二参考电流。响应于控制信号，开关选择性地将第一和第二参考电流中的一个提供给第二端子。第一和第二参考字线电压对应于不同的电压电平。

6. 发明申请

US20110055670A1 Programming Method and Memory Device Using the Same 有权
标题翻译：编程方法和使用它的存储设备
公开(公告)号：US20110055670A1
公开(公告)日：2011-03-03
申请号：US12943443
申请日：2010-11-10
申请人： Chun-Hsiung Hung , Hsin-Yi Ho
发明人： Chun-Hsiung Hung , Hsin-Yi Ho
IPC分类号： G11C11/40 , G11C7/00 , G06F11/07
CPC分类号： G11C16/3404 , G11C16/3454
摘要： A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command.
摘要翻译：提供了一种应用于存储器的编程方法。存储器包括多个存储单元。该方法包括以下步骤。响应于第一编程命令对存储器单元的目标单元进行编程。响应于第二编程命令对目标单元进行编程。

7. 发明授权

US07580292B2 Method for programming a multilevel memory 有权
标题翻译：多级存储器编程方法
公开(公告)号：US07580292B2
公开(公告)日：2009-08-25
申请号：US11812033
申请日：2007-06-14
申请人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
发明人： Hsin-Yi Ho , Nian-Kai Zous , I-Jen Huang , Yung-Feng Lin
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5671 , G11C2211/5621
摘要： A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL−K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.
摘要翻译：提供了一种用于编程MLC存储器的方法。 MLC存储器有多个位，每个位都有多个编程状态。每个编程状态具有第一PV级别。该方法包括（a）通过使用Vd偏置BL将具有低于目标编程状态的PV电平的Vt电平的存储器的位编程为编程位; （b）如果存储器的每个位的Vt电平不低于目标编程状态的PV电平，则结束该方法，否则继续步骤（c）; 以及（c）设定BL = BL + K1，并且如果每个编程的比特都具有低于PV水平的Vt级别，而设置BL = BL-K2，并重复步骤（a），如果在至少一个编程位的Vt电平不低于PV电平。

8. 发明申请

US20080137427A1 Programming scheme for non-volatile flash memory 有权
标题翻译：非易失性闪存的编程方案
公开(公告)号：US20080137427A1
公开(公告)日：2008-06-12
申请号：US11636920
申请日：2006-12-11
申请人： Chun-Jen Huang , Chia-Jung Chen , Hsin-Yi Ho
发明人： Chun-Jen Huang , Chia-Jung Chen , Hsin-Yi Ho
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5621
摘要： An embodiment of the present invention involves a method of programming a memory cell. The memory cell is in a first state having a maximum initial threshold voltage. The memory cell is to be programmed to one of a plurality of states having a higher target threshold voltage relative to the maximum initial threshold voltage. There is a cue voltage between the maximum initial threshold voltage and the target threshold voltage. The memory cell has a drain region. The method includes applying a drain voltage to the cell by a programming pulse having a first width, determining whether the cell has reached the cue threshold voltage, and if the cell has reached the cue threshold voltage, changing the programming pulse width from the first pulse width to a second pulse width. The second pulse width is smaller than the first pulse width.
摘要翻译：本发明的一个实施例涉及一种编程存储器单元的方法。存储单元处于具有最大初始阈值电压的第一状态。存储器单元将被编程为具有相对于最大初始阈值电压的较高目标阈值电压的多个状态之一。在最大初始阈值电压和目标阈值电压之间存在一个提示电压。存储单元具有漏极区域。该方法包括通过具有第一宽度的编程脉冲向单元施加漏极电压，确定单元是否已经达到提示阈值电压，以及如果单元已经达到提示阈值电压，则从第一脉冲改变编程脉冲宽度宽度到第二个脉冲宽度。第二脉冲宽度小于第一脉冲宽度。

9. 发明申请

US20050149664A1 Method for verifying a programmed flash memory 有权
标题翻译：用于验证编程闪存的方法
公开(公告)号：US20050149664A1
公开(公告)日：2005-07-07
申请号：US10962588
申请日：2004-10-13
申请人： Ming-Hung Chou , Hsin-Yi Ho
发明人： Ming-Hung Chou , Hsin-Yi Ho
IPC分类号： G11C11/34 , G11C16/34
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A method for verifying a programmed flash memory. When reading a memory cell, a voltage applied to a drain of the memory cell is a read drain voltage. First, a word line is enabled by applying a verification gate voltage. Next, a first bit line, which is connected to the drain of the memory cell, is enabled and a verification drain voltage, which is higher than the read drain voltage, is applied to the first bit line. Then, a second bit line is enabled and grounded. Thereafter, a third bit line is enabled and a verification isolation voltage is applied. Then, a drain current of the first bit line is sensed, wherein the drain current flows through the first bit line, the memory cell, and the second bit line. Finally, it is judged whether or not the memory cell is successfully programmed according to the drain current.
摘要翻译：一种验证编程闪存的方法。当读取存储单元时，施加到存储单元的漏极的电压是读取漏极电压。首先，通过应用验证门电压来启用字线。接下来，连接到存储单元的漏极的第一位线被使能，并且将高于读取的漏极电压的验证漏极电压施加到第一位线。然后，第二位线被使能并接地。此后，启用第三位线并施加验证隔离电压。然后，感测第一位线的漏极电流，其中漏极电流流过第一位线，存储器单元和第二位线。最后，根据漏极电流判断存储单元是否成功编程。

10. 发明授权

US06845052B1 Dual reference cell sensing scheme for non-volatile memory 有权
标题翻译：用于非易失性存储器的双参考单元感测方案
公开(公告)号：US06845052B1
公开(公告)日：2005-01-18
申请号：US10250040
申请日：2003-05-30
申请人： Hsin-Yi Ho , Nai-Ping Kuo , Chun-Hsiung Hung , Gin-Liang Chen , Wen-Chiao Ho , Ho-Chun Liou
发明人： Hsin-Yi Ho , Nai-Ping Kuo , Chun-Hsiung Hung , Gin-Liang Chen , Wen-Chiao Ho , Ho-Chun Liou
IPC分类号： G11C7/06 , G11C7/14 , G11C16/28 , G11C7/02
CPC分类号： G11C7/14 , G11C7/062 , G11C16/28 , G11C2207/2227
摘要： The present invention provides a dual reference cell sensing scheme for non-volatile memory. A high voltage reference cell and a low voltage reference cell are individually coupled to two sense amplifiers for providing two distinct reference voltages for comparison against the memory cell voltage. The output of the two sense amplifiers is further connected to a second stage sense amplifier to determine the status of the memory. The dual reference cell sensing scheme provides an increased sensing window which increases performance under low voltage application. The dual reference cell sensing scheme can be implemented by either voltage-based, current-based, or ground.
摘要翻译：本发明提供了一种用于非易失性存储器的双参考单元感测方案。高电压参考单元和低电压参考单元分别耦合到两个读出放大器，用于提供用于与存储单元电压进行比较的两个不同的参考电压。两个读出放大器的输出进一步连接到第二级读出放大器以确定存储器的状态。双参考电池感测方案提供增加的感测窗口，其在低电压应用下增加性能。双参考电池感测方案可以通过基于电压，基于电流或接地来实现。

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