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1. 发明授权

US5241506A Semiconductor memory circuit apparatus 失效
标题翻译：半导体存储器电路设备
公开(公告)号：US5241506A
公开(公告)日：1993-08-31
申请号：US612459
申请日：1990-11-14
申请人： Hiroyuki Motegi , Hideaki Uchida , Yasunori Kuwashima
发明人： Hiroyuki Motegi , Hideaki Uchida , Yasunori Kuwashima
IPC分类号： G11C11/419 , G11C7/14 , G11C11/401 , G11C11/407 , G11C11/409
CPC分类号： G11C7/14
摘要： A random access memory (RAM) array has a dummy word line having a similar pattern to the word lines provided for the RAM cells. A transistor having the same channel width and channel length as one of the transistors in the RAM cells has its gate connected to the dummy word line. An inverter is formed of three transistors including the transistor having its gate connected to the dummy word line, with the output of the inverter connected to a capacitor. The capacitance of the capacitor is set close to the capacitance of a bus line of the RAM to adjust the dummy word line and the word lines of the RAM circuits to have the same transfer delay. If the capacitance of the capacitor is made slightly smaller than the bus line capacitance, the potential at the output of the inverter can be changed by this difference. The output of the inverter is detected, and can be used as a drive signal to drive a sense amplifier used to read the RAM cells. Further, the signal traveling through the dummy word line can be used as a precharge signal.

2. 发明授权

US5343221A Power supply apparatus used for driving liquid-crystal display and capable of producing a plurality of electrode-driving voltages of intermediate levels 失效
标题翻译：用于驱动液晶显示器并且能够产生中间电平的多个电极驱动电压的电源装置
公开(公告)号：US5343221A
公开(公告)日：1994-08-30
申请号：US82429
申请日：1993-06-25
申请人： Takashi Arakawa , Hiroyuki Motegi
发明人： Takashi Arakawa , Hiroyuki Motegi
IPC分类号： G02F1/133 , G09G3/36 , G09G3/00
CPC分类号： G09G3/3696
摘要： A plurality of resistors serially connected with each other between a maximum voltage level "V" and a minimum voltage level "0" are provided to generate voltage-divided intermediate voltage levels "V2H", "V1H", "V3L", "V2L", the voltages having the voltage-divided intermediate voltage levels being supplied to a first group of operational amplifiers whose first stage input portions are formed of N-channel MOSFETs and a second group of operational amplifiers whose first stage input portions are formed of P-channel MOSFETs. Frame signal FR for alternating-current-driving a liquid crystal display device is supplied to the operational amplifiers. When signal FR is in a state "0", the first group of operational amplifiers are brought into an active state while the second group is brought into an inactive state. When signal FR is in a state "1", the first group of operational amplifiers are inactive. Under the condition that power down signal PD for non-use of the liquid crystal display device is generated, all of the operational amplifiers are controlled to be in an inactive state.
摘要翻译：提供在最大电压电平“V”和最小电压电平“0”之间串联连接的多个电阻器，以产生分压中间电压电平“V2H”，“V1H”，“V3L”，“V2L” 具有分压中间电压电平的电压被提供给第一组运算放大器，其第一级输入部分由N沟道MOSFET形成，第二组运算放大器的第一级输入部分由P沟道 MOSFET。用于将液晶显示装置进行交流驱动的帧信号FR提供给运算放大器。当信号FR处于状态“0”时，第一组运算放大器处于活动状态，而第二组处于非活动状态。当信号FR处于状态“1”时，第一组运算放大器是无效的。在产生用于不使用液晶显示装置的掉电信号PD的条件下，所有的运算放大器都被控制在无效状态。

3. 发明授权

US6025822A Driving device, a column electrode driving semiconductor integrated circuit and a row electrode driving semiconductor integrated circuit used for a liquid crystal display device 失效
标题翻译：驱动装置，列电极驱动半导体集成电路和用于液晶显示装置的行电极驱动半导体集成电路
公开(公告)号：US6025822A
公开(公告)日：2000-02-15
申请号：US859033
申请日：1997-05-20
申请人： Hiroyuki Motegi , Takeshi Kuwata , Yutaka Nakagawa , Akira Nakazawa
发明人： Hiroyuki Motegi , Takeshi Kuwata , Yutaka Nakagawa , Akira Nakazawa
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G11C11/401
CPC分类号： G09G3/3625 , G09G3/3681 , G09G3/3692 , G09G2310/0208 , G09G2320/0606 , G09G2320/0673 , G09G3/2018 , G09G5/393 , G09G5/395
摘要： A column electrode driving semiconductor integrated circuit for driving column electrodes in a liquid crystal display device to be driven by a multiple line selection method wherein the liquid crystal display device has a select and output circuit which selects a specified voltage value among voltage values having the member of levels corresponding to the member of simultaneously selected row electrodes, and applies the selected voltage value to each column electrode, wherein a memory unit including a control circuit stores display data and outputs the data on each row electrode in simultaneously selected lines, and an arithmetic circuit unit including an arithmetic processing circuit receives the data outputted from the memory unit and selection data indicating a voltage pattern applied to a selected row electrode and produces by arithmetic processing information of voltages selected by the select and output circuit unit.
摘要翻译：一种用于驱动液晶显示装置中的列电极的列电极驱动半导体集成电路，以通过多线选择方法驱动，其中液晶显示装置具有选择和输出电路，其选择具有该部件的电压值中的指定电压值的电位对应于同时选择的行电极的成员，并且将所选择的电压值施加到每个列电极，其中包括控制电路的存储单元存储显示数据并且以同时选择的行输出每行行电极上的数据，以及算术包括算术处理电路的电路单元接收从存储器单元输出的数据和指示施加到所选行电极的电压模式的选择数据，并通过由选择和输出电路单元选择的电压的算术处理信息产生。

4. 发明授权

US5953002A Driving method for a liquid crystal display device 失效
标题翻译：液晶显示装置的驱动方法
公开(公告)号：US5953002A
公开(公告)日：1999-09-14
申请号：US628634
申请日：1996-04-17
申请人： Yoshinori Hirai , Akira Nakazawa , Makoto Nagai , Takeshi Kuwata , Hiroyuki Motegi , Kazuyoshi Kawaguchi
发明人： Yoshinori Hirai , Akira Nakazawa , Makoto Nagai , Takeshi Kuwata , Hiroyuki Motegi , Kazuyoshi Kawaguchi
IPC分类号： G09G3/20 , G09G3/36 , G09G5/00
CPC分类号： G09G3/2011 , G09G3/3622 , G09G3/3625 , G09G3/2018
摘要： A driving method for a direct addressing type liquid crystal display device for displaying gradation by changing the amplitude of voltages applied to pixels, wherein a series of voltage pulses, as signal voltages, composed of a plurality of different voltage levels are applied in order to display a specified gradation, and for a display, a plurality kinds of gradation in which a part of the voltage levels is commonly used are selected.
摘要翻译： PCT No.PCT / JP95 / 01656 Sec。 371日期：1996年4月17日 102（e）日期1996年4月17日PCT提交1995年8月22日PCT公布。出版物WO96 / 06423 日期：1996年2月29日，一种用于通过改变施加到像素的电压的幅度来显示灰度的直接寻址型液晶显示装置的驱动方法，其中由多个不同电压电平组成的一系列电压脉冲作为信号电压是应用以显示指定的灰度，并且对于显示，选择其中一部分电压电平被共同使用的多种灰度。

5. 发明授权

US5455534A Semiconductor device for liquid crystal panel driving power supply 失效
标题翻译：液晶面板驱动电源半导体装置
公开(公告)号：US5455534A
公开(公告)日：1995-10-03
申请号：US17381
申请日：1993-02-12
申请人： Hiroyuki Motegi , Takeshi Nakashiro
发明人： Hiroyuki Motegi , Takeshi Nakashiro
IPC分类号： G02F1/133 , G05F3/24 , G05F3/26 , G09G3/18 , G09G3/36 , G05F1/10 , G06F3/14
CPC分类号： G09G3/3696 , G05F3/242 , G05F3/262 , G09G2330/02
摘要： A semiconductor device for a liquid crystal panel driving power supply in which a first reference voltage is converted in impedance by an operational amplifier to output it as a second reference voltage, comprising control means wherein, in a suitable fixed period during a period of displaying a liquid crystal, the current supply capacity of said operational amplifier is enhanced, and, in another period during said period of displaying a liquid crystal, the current supply capacity of said operational amplifier is lowered.
摘要翻译：一种用于液晶面板驱动电源的半导体器件，其中通过运算放大器将第一参考电压转换成阻抗以将其作为第二参考电压输出，包括控制装置，其中在显示期间的适当的固定周期内液晶，所以运算放大器的电流供应能力得到提高，而在所述液晶显示期间的另一期间，所述运算放大器的电流供应能力降低。

6. 发明授权

US5221863A Phase-locked loop clock signal generator 失效
标题翻译：相位锁定环路时钟信号发生器
公开(公告)号：US5221863A
公开(公告)日：1993-06-22
申请号：US749184
申请日：1991-08-23
申请人： Hiroyuki Motegi
发明人： Hiroyuki Motegi
IPC分类号： H03H11/26 , H03K5/00 , H03K5/13 , H03L7/00 , H03L7/081
CPC分类号： H03L7/081 , H03K5/133 , H03K2005/0013 , H03K2005/00195
摘要： A variable delay circuit delays an input signal by an amount corresponding to a control signal. A signal delay amount of the variable delay circuit is detected by a delay amount detector circuit, and the detection signal is supplied to a charge pump circuit. In the charge pump circuit 12, a DC voltage according to a pulse width ratio of the input signal to an detection output from the delay amount detector circuit is generated and fed back to the variable delay circuit as the control signal. A predetermined DC voltage output from an initial voltage setting circuit is applied to a path of the control signal output from the charge pump circuit 12. An output voltage from the initial voltage setting circuit is set to be an approximate value of a value such that a desired delay amount is obtained in each of delay stages of the variable delay circuit, and the initial voltage setting circuit sets an initial value of the control signal.

7. 发明授权

US5059838A Signal delay circuit using charge pump circuit 失效
标题翻译：使用充电泵电路的信号延迟电路
公开(公告)号：US5059838A
公开(公告)日：1991-10-22
申请号：US466472
申请日：1990-01-17
申请人： Hiroyuki Motegi , Kenji Matsuo , Akira Nagae , Hideaki Uchida
发明人： Hiroyuki Motegi , Kenji Matsuo , Akira Nagae , Hideaki Uchida
IPC分类号： H03K5/135 , G11C11/4076 , H03K5/00 , H03K5/133 , H03K5/134 , H03K19/003 , H03L7/00
CPC分类号： H03K5/133 , H03K19/00323 , H03K2005/00097 , H03K2005/0013 , H03K2005/00195
摘要： A delay circuit delays an input signal having a predetermined frequency by a time corresponding to a control signal. A delay amount detector detects a signal delay amount of the delay circuit. A charge pump circuit generates a DC voltage corresponding to a pulse width ratio between the input signal and a detection signal of the delay amount detector. This DC voltage is fed back to the delay circuit as a control signal.

8. 发明授权

US4912433A VCO controlled by separate phase locked loop 失效
标题翻译： VCO由单独的锁相环控制
公开(公告)号：US4912433A
公开(公告)日：1990-03-27
申请号：US352540
申请日：1989-05-16
申请人： Hiroyuki Motegi , Hiroki Muroga , Satoshi Suzuki
发明人： Hiroyuki Motegi , Hiroki Muroga , Satoshi Suzuki
IPC分类号： H03L7/18 , H03K3/03 , H03K3/354 , H03K7/06 , H03L7/081 , H03L7/099
CPC分类号： H03L7/0805 , H03K3/0315 , H03K7/06 , H03L7/081
摘要： A voltage controlled oscillator (VCO) is controlled by a separate phase locked loop (PLL). The PLL includes a first variable delay circuit of m stages which receives a reference frequency signal and produces a delayed signal which is compared in a phase comparator with the reference frequency signal. A first control signal generating circuit in the PLL receives the output of the phase comparator and a reference voltage to produce a first control signal for controlling the delay of the first variable delay circuit. The VCO contains a ring oscillator formed of a second variable delay circuit of n stages similar to those of the first variable delay circuit. A second control signal generating circuit in the VCO receives the output of the phase comparator and a control voltage to produce a second control signal for controlling the delay of the second variable delay circuit to thereby control the output frequency of the VCO.

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