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1. 发明授权

US5926065A Digital modulator having a digital filter including low-speed circuit components 失效
标题翻译：具有包括低速电路元件的数字滤波器的数字调制器
公开(公告)号：US5926065A
公开(公告)日：1999-07-20
申请号：US947348
申请日：1997-10-08
申请人： Hirotake Wakai , Makoto Ohnishi , Fumihito Tomaru
发明人： Hirotake Wakai , Makoto Ohnishi , Fumihito Tomaru
IPC分类号： H04L27/00 , H03D3/00 , H03H17/06 , H04L27/38 , H04L27/22
CPC分类号： H04L27/3854 , H03D3/006 , H03H17/06
摘要： A digital demodulator which demodulates an analog signal obtained through a quadrature amplitude modulation to produce a digital demodulated signal includes a converter to convert the analog signal into a digital signal and a signal processor to quadrature-demodulating the digital signal from the converter. Assuming that the analog signal has a carrier frequency of f.sub.IF and the signal conversion is accomplished with the sampling frequency fs, the demodulator is set to satisfy fs=4.multidot.f.sub.IF /(2n+1), where n denotes a positive integer. The signal processing section conducts the quadrature demodulation according to a quadrature local oscillation signal having a frequency fc satisfying fc=fs/4.
摘要翻译：解调通过正交幅度调制获得的模拟信号以产生数字解调信号的数字解调器包括将模拟信号转换为数字信号的转换器和信号处理器以对来自转换器的数字信号进行正交解调。假设模拟信号具有fIF的载波频率并以采样频率fs完成信号转换，则解调器被设置为满足fs = 4xfIF /（2n + 1），其中n表示正整数。信号处理部根据具有满足fc = fs / 4的频率fc的正交本地振荡信号进行正交解调。

2. 发明申请

US20090034479A1 Network system, control method, and gateway 审中-公开
标题翻译：网络系统，控制方式和网关
公开(公告)号：US20090034479A1
公开(公告)日：2009-02-05
申请号：US12219258
申请日：2008-07-18
申请人： Koji Wakayama , Hirotake Wakai
发明人： Koji Wakayama , Hirotake Wakai
IPC分类号： H04Q7/00
CPC分类号： H04W36/02 , H04L45/16 , H04W36/0007 , H04W72/005
摘要： To prevent a packet loss during hand over, provided is a network system including: a gateway coupled with a wired network; and at least two base stations coupled with the gateway over the wired network and providing a wireless access method, in which the gateway is configured to: calculate, for each of the at least two base stations, a delay in information transmission between the gateway and each of the at least two base stations; choose a maximum delay from among the calculated delays of each of the at least two base stations; calculate, as a delay difference of each of the at least two base stations, a difference between the chosen maximum delay and the delay of each of the at least two base stations; and notify each of the at least two base stations of the calculated delay difference of each of the at least two base stations.
摘要翻译：为了防止在切换期间的分组丢失，提供了一种网络系统，包括：与有线网络耦合的网关; 以及至少两个基站，其经由所述有线网络与所述网关耦合并且提供无线接入方法，其中所述网关被配置为：针对所述至少两个基站中的每一个，计算所述网关与所述网关之间的信息传输的延迟所述至少两个基站中的每一个; 从所述至少两个基站中的每一个的所计算的延迟中选择最大延迟; 作为所述至少两个基站中的每一个的延迟差，计算所选择的最大延迟与所述至少两个基站中的每一个的所述延迟之间的差; 并且向所述至少两个基站中的每一个通知所述至少两个基站中的每一个的所计算的延迟差。

3. 发明申请

US20070223505A1 DATA TRANSMISSION APPARATUS, DATA TRANSMISSION METHOD AND DATA TRANSMISSION SYSTEM 审中-公开
标题翻译：数据传输设备，数据传输方法和数据传输系统
公开(公告)号：US20070223505A1
公开(公告)日：2007-09-27
申请号：US11677694
申请日：2007-02-22
申请人： Kimio ITAI , Yoshikuni Ito , Hirotake Wakai
发明人： Kimio ITAI , Yoshikuni Ito , Hirotake Wakai
IPC分类号： H04L12/56 , H04L12/54
CPC分类号： H04L47/10 , H04L47/14 , H04L47/22 , H04L47/50 , H04L47/522 , H04L49/90 , H04L49/901
摘要： A data transmission apparatus is disclosed, which includes a first terminal for use with variable-rate data, a second terminal for use with constant-rate data, a processing unit for input of data from the first and second terminals, a modulator unit for modulating the output of the processor unit, a control unit for controlling the modulator, and a transmitter unit. The processor has a first buffer for writing thereinto data from the first terminal, a second buffer for writing therein data from the second terminal, and a selector for reading data from either one of the first and second buffers while switching therebetween at a predetermined rate, thereby allowing the switching of the selector to be performed under the control of the control unit.
摘要翻译：公开了一种数据传输装置，其包括与可变速率数据一起使用的第一终端，用于使用恒定速率数据的第二终端，用于从第一和第二终端输入数据的处理单元，用于调制处理器单元的输出，用于控制调制器的控制单元和发送器单元。处理器具有用于从第一终端写入数据的第一缓冲器，用于在其中写入来自第二终端的数据的第二缓冲器，以及用于以预定速率在其间切换之间从第一和第二缓冲器中的任一个读取数据的选择器，从而允许在控制单元的控制下执行选择器的切换。

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