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1. 发明授权

US07506749B2 Conveying system 有权
标题翻译：输送系统
公开(公告)号：US07506749B2
公开(公告)日：2009-03-24
申请号：US11730981
申请日：2007-04-05
申请人： Hiroshi Fukazawa , Masazumi Fukushima , Makoto Yamamoto
发明人： Hiroshi Fukazawa , Masazumi Fukushima , Makoto Yamamoto
IPC分类号： B65G47/18
CPC分类号： H01L21/68707 , H01L21/67155 , H01L21/67376 , H01L21/67383 , H01L21/67772 , H01L21/67781
摘要： The present invention provides a conveying system that performs efficient conveyance by using trays each accommodating one workpiece, as a basic conveyor, and fully utilizing this advantage of the trays to allow its conveyance form to be changed as required. The conveying system includes a single-pod conveyor 10 for conveying pods 5 one by one, a pod stacker 50 for stacking a plurality of pods 5, a stacked pod conveyor 60 for conveying the stacked pods 5, and a pod destacker 50 for destacking the stacked pods.
摘要翻译：本发明提供一种输送系统，其通过使用容纳一个工件的托盘作为基本输送机进行有效的输送，并且充分利用托盘的这种优点以允许根据需要改变其输送形式。输送系统包括用于一个接一个地输送荚果5的单荚式输送机10，用于堆叠多个豆荚5的荚果堆垛机50，用于输送堆叠的豆荚5的堆叠的豆荚输送机60，以及用于破坏堆叠的pod。

2. 发明授权

US06655588B2 Card system, IC card and card reader/writer used for the card system 失效
标题翻译：用于卡片系统的卡片系统，IC卡和读卡器/写卡器
公开(公告)号：US06655588B2
公开(公告)日：2003-12-02
申请号：US09916944
申请日：2001-07-27
申请人： Hiroshi Fukazawa
发明人： Hiroshi Fukazawa
IPC分类号： G06K500
CPC分类号： H04L1/1867 , G06K7/0013 , G06K7/10297 , H04L1/0063 , H04L1/1692 , H04L1/1803
摘要： A card system having an IC card and a card reader/writer wherein when data is transmitted and received over a signal line between the IC card and the card reader/writer for reading or writing of the data, a data transmitting side transmits a parity based upon content of the data together with the data over the signal line and a data receiving side checks whether or not there is any error in reception of data based upon content of the a data and the parity received to transmit back to the data transmitting side a data retransmission request signal for requesting the data transmitting side to retransmit the data when there is an error; and wherein the IC card corrects a level of the signal line for requesting the data transmitting side to transmit next data when it is verified that there is no error in the reception of the data based upon content of the data and the parity received by the data receiving side.
摘要翻译：一种具有IC卡和读卡器/写入器的卡系统，其中当通过IC卡与读卡器/写卡器之间的信号线发送和接收数据以读取或写入数据时，数据发送侧发送基于奇偶校验一旦数据内容与信号线上的数据一起，并且数据接收侧根据数据的内容和接收到的发送回数据发送侧的奇偶校验来检查数据的接收是否有错误数据重传请求信号，用于在存在错误时请求数据发送侧重传数据; 并且其中当基于所述数据的内容和由所述数据接收到的所述奇偶校验验证所述数据的接收中没有错误时，所述IC卡校正用于请求所述数据发送侧发送下一数据的信号线的电平接收方。

3. 发明申请

US20070292256A1 Conveying system 审中-公开
标题翻译：输送系统
公开(公告)号：US20070292256A1
公开(公告)日：2007-12-20
申请号：US11730768
申请日：2007-04-04
申请人： Hiroshi Fukazawa , Masazumi Fukushima , Makoto Yamamoto
发明人： Hiroshi Fukazawa , Masazumi Fukushima , Makoto Yamamoto
IPC分类号： B65G60/00
CPC分类号： H01L21/67781 , H01L21/67155 , H01L21/67772 , H01L21/68707
摘要： The present invention provides a conveying system that enables the automation of handling of each tray, the handling of multiproduct small lots, and the improvement of conveying efficiency, while maintaining cleanliness. The conveying system has a tray loading and unloading means 20 for loading and unloading a plurality of stacked trays 1 into and from a pod 5 and a pod conveying means 10 for conveying the pod 5.
摘要翻译：本发明提供一种输送系统，其能够在保持清洁的同时，实现每个托盘的自动化处理，多产品小批量的处理以及提高输送效率。输送系统具有托盘装载和卸载装置20，用于将多个堆叠的托盘1装载到和从托架5中卸载和从托架5卸载多个托盘1和用于输送托架5的托盘输送装置10。

4. 发明申请

US20070289844A1 Conveying system 有权
标题翻译：输送系统
公开(公告)号：US20070289844A1
公开(公告)日：2007-12-20
申请号：US11730981
申请日：2007-04-05
申请人： Hiroshi Fukazawa , Masazumi Fukushima , Makoto Yamamoto
发明人： Hiroshi Fukazawa , Masazumi Fukushima , Makoto Yamamoto
IPC分类号： B65G1/04
CPC分类号： H01L21/68707 , H01L21/67155 , H01L21/67376 , H01L21/67383 , H01L21/67772 , H01L21/67781
摘要： The present invention provides a conveying system that performs efficient conveyance by using trays each accommodating one workpiece, as basic conveying means, and fully utilizing this advantage of the trays to allow its conveyance form to be changed as required. The conveying system includes a single-pod conveying means 10 for conveying pods 5 one by one, a pod stacking means 50 for stacking a plurality of pods 5, a stacked pod conveying means 60 for conveying the stacked pods 5, and a pod destacking means 50 for destacking the stacked pods.
摘要翻译：本发明提供一种输送系统，其通过使用容纳一个工件的托盘作为基本输送装置进行有效的输送，并且充分利用托盘的这种优点，以允许根据需要改变其输送形式。输送系统包括一个一个一个地输送箱体5的单个荚输送装置10，用于堆叠多个荚果的荚堆叠装置5，一个用于输送堆叠的荚果5的堆叠的荚输送装置60，以及一个荚的破坏装置 50用于破坏堆叠的荚。

5. 发明授权

US06338676B1 Air conditioner 有权
公开(公告)号：US06338676B1
公开(公告)日：2002-01-15
申请号：US09471473
申请日：1999-12-23
申请人： Masakazu Kondou , Jun Kitamura , Takahiro Murayama , Motoo Sano , Shinichi Suzuki , Hiroaki Ishikawa , Akira Takamori , Hiroshi Fukazawa
发明人： Masakazu Kondou , Jun Kitamura , Takahiro Murayama , Motoo Sano , Shinichi Suzuki , Hiroaki Ishikawa , Akira Takamori , Hiroshi Fukazawa
IPC分类号： F24F102
CPC分类号： F24F1/027 , F24F1/0007 , F24F1/0011 , F24F13/22 , F24F2001/0048
摘要： Inside a blown-out air duct in the air conditioner through which conditioned air reaches a blowing-out port, there is provided a rectifying box having a air passage therein, for rectifying a flow of the conditioned air toward a predetermined flowing direction in order to prevent any dew condensation at the blowing-out port in the air conditioner. In the meantime, in order to suppress noise, rectifying plates for reducing an inflowing angle of air flowing into the fin tips of a heat exchanger are interposed between an axial fan and the heat exchanger for taking in the air from the axial fan for heat exchanging.

6. 发明授权

US07877577B2 Information processor and instruction fetch control method 有权
标题翻译：信息处理器和指令获取控制方法
公开(公告)号：US07877577B2
公开(公告)日：2011-01-25
申请号：US12000164
申请日：2007-12-10
申请人： Hiroshi Fukazawa
发明人： Hiroshi Fukazawa
IPC分类号： G06F9/24
CPC分类号： G06F9/3804 , G06F9/30058
摘要： In implementing an encryption algorithm or the like in a computer, it is difficult to align timing at which an instruction is executed regardless of presence or absence of branch in a case of including a conditional branch instruction. In order to solve the problem, provided is an information processor (1), including: an instruction fetch unit (instruction fetch circuit 200) that fetches an instruction code to be executed to output the fetched instruction code; and an instruction decode unit (instruction decode circuit 300) that decodes the instruction code that is output from the instruction fetch unit, in which the instruction decode unit outputs, upon detection of the instruction code being a conditional branch instruction, a control signal to the instruction fetch unit so that fetch timing of the successive instruction code becomes identical with each other regardless of the presence or absence of the branch due to the branch condition.
摘要翻译：在计算机中实现加密算法等时，无论在包含条件转移指令的情况下，是否存在分支，都难以对准执行指令的定时。为了解决该问题，提供了一种信息处理器（1），其包括：取指令单元（指令获取电路200），其取出要执行的指令代码以输出所提取的指令代码; 以及指令解码单元（指令解码电路300），其在指示解码单元输出的指令获取单元输出的指令代码被检测到作为条件转移指令的指令代码时，将控制信号转换为指令提取单元，使得连续指令代码的提取定时彼此相同，而不管由于分支条件是否存在分支。

7. 发明申请

US20100005131A1 Power-residue calculating unit and method of controlling the same 审中-公开
标题翻译：功率残差计算单元及其控制方法
公开(公告)号：US20100005131A1
公开(公告)日：2010-01-07
申请号：US12213319
申请日：2008-06-18
申请人： Hiroshi Fukazawa
发明人： Hiroshi Fukazawa
IPC分类号： G06F7/72 , G06F7/52
CPC分类号： H04L9/302 , H04L9/003 , H04L9/005 , H04L2209/122 , H04L2209/127
摘要： A power-residue calculating unit according to one embodiment of the present invention includes a multiplication residue calculating unit performing a multiplication calculation and a residue calculation based on a multiplicand, a multiplier, and a divisor, a power storing portion separately storing value of each bit when a power is shown by a binary number, a first selecting circuit outputting one of an output of the multiplication residue calculating unit and the multiplicand depending on the value of the bit that is referred, and a result storing register storing an output value of the first selecting circuit as a calculation result.
摘要翻译：根据本发明的一个实施例的功率残差计算单元包括乘法残差计算单元，其执行乘法运算和基于乘法器，乘法器和除数的残差计算，分别存储每个位的值的功率存储单元当以二进制数表示功率时，第一选择电路根据所参考的比特的值输出乘法残差计算单元的输出和被乘数的输出之一，以及存储存储输入值的结果存储寄存器第一选择电路作为计算结果。

8. 发明申请

US20080140995A1 Information processor and instruction fetch control method 有权
标题翻译：信息处理器和指令获取控制方法
公开(公告)号：US20080140995A1
公开(公告)日：2008-06-12
申请号：US12000164
申请日：2007-12-10
申请人： Hiroshi Fukazawa
发明人： Hiroshi Fukazawa
IPC分类号： G06F9/312
CPC分类号： G06F9/3804 , G06F9/30058
摘要： In implementing an encryption algorithm or the like in a computer, it is difficult to align timing at which an instruction is executed regardless of presence or absence of branch in a case of including a conditional branch instruction. In order to solve the problem, provided is an information processor (1), including: an instruction fetch unit (instruction fetch circuit 200) that fetches an instruction code to be executed to output the fetched instruction code; and an instruction decode unit (instruction decode circuit 300) that decodes the instruction code that is output from the instruction fetch unit, in which the instruction decode unit outputs, upon detection of the instruction code being a conditional branch instruction, a control signal to the instruction fetch unit so that fetch timing of the successive instruction code becomes identical with each other regardless of the presence or absence of the branch due to the branch condition.
摘要翻译：在计算机中实现加密算法等时，无论在包含条件转移指令的情况下，是否存在分支，都难以对准执行指令的定时。为了解决该问题，提供了一种信息处理器（1），其包括：取指令单元（指令获取电路200），其取出要执行的指令代码以输出所提取的指令代码; 以及指令解码单元（指令解码电路300），其在指示解码单元输出的指令获取单元输出的指令代码被检测到作为条件转移指令的指令代码时，将控制信号转换为指令提取单元，使得连续指令代码的提取定时彼此相同，而不管由于分支条件是否存在分支。

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