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1. 发明申请

US20120146154A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120146154A1
公开(公告)日：2012-06-14
申请号：US13399102
申请日：2012-02-17
申请人： SATORU ITOU , HIROMASA FUJIMOTO , SUSUMU AKAMATSU , TOSHIE KUTSUNAI
发明人： SATORU ITOU , HIROMASA FUJIMOTO , SUSUMU AKAMATSU , TOSHIE KUTSUNAI
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes a first and a second MIS transistor. The first and second MIS transistors include a first and a second gate electrode formed on a first and a second active region with a first and a second gate insulating film being formed therebetween, first and second sidewalls including a first and a second inner sidewall formed on side surfaces of the first and second gate electrodes and having an L-shaped cross-section, and first and second source/drain regions formed in the first and second active regions laterally outside the first and second sidewalls. The first source/drain regions include a silicon compound layer formed in trenches provided in the first active region and causes a first stress in a gate length direction of a channel region in the first active region. A width of the first inner sidewall is smaller than a width of the second inner sidewall.
摘要翻译：半导体器件包括第一和第二MIS晶体管。第一和第二MIS晶体管包括形成在第一和第二有源区上的第一和第二栅电极，其间形成有第一和第二栅极绝缘膜，第一和第二侧壁包括形成在第一和第二内侧壁上的第一和第二内侧壁所述第一和第二栅电极的侧表面具有L形横截面，以及在所述第一和第二有源区中形成在所述第一和第二侧壁的横向外侧的第一和第二源/漏区。第一源极/漏极区域包括形成在设置在第一有源区域中的沟槽中的硅化合物层，并且在第一有源区域中的沟道区域的栅极长度方向上产生第一应力。第一内侧壁的宽度小于第二内侧壁的宽度。

2. 发明授权

US07932141B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07932141B2
公开(公告)日：2011-04-26
申请号：US12164635
申请日：2008-06-30
申请人： Kentaro Nakanishi , Hiromasa Fujimoto , Takayuki Yamada
发明人： Kentaro Nakanishi , Hiromasa Fujimoto , Takayuki Yamada
IPC分类号： H01L21/3205
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.
摘要翻译：半导体器件包括n型MIS晶体管和p型MIS晶体管。 n型MIS晶体管包括形成在第一有源区上的第一栅电极和形成在第一栅电极的侧面上的第一侧壁。 p型MIS晶体管包括形成在第二有源区上的第二栅电极，形成在第二栅电极的侧面上的第二侧壁和形成在第二有源区中的应变层。第二侧壁具有比第一侧壁更小的厚度。

3. 发明授权

US06830973B2 Nonvolatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06830973B2
公开(公告)日：2004-12-14
申请号：US10238636
申请日：2002-09-11
申请人： Hiromasa Fujimoto , Fumihiko Noro , Masataka Kusumi
发明人： Hiromasa Fujimoto , Fumihiko Noro , Masataka Kusumi
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： Using a rapid thermal oxidation device, the top and side surfaces of a floating gate electrode are oxidized by In Situ Steam Generation (ISSG), wherein oxygen to which about 0.5 to 33% hydrogen has been added is introduced directly into a chamber with a temperature of approximately 900 to 1100° C. and a pressure of approximately 1,000 to 2,000 Pa, in order to generate water vapor from the introduced hydrogen and oxygen on a heated semiconductor substrate. Thus, an insulating film made of silicon oxide is formed on the surface of the floating gate electrode.
摘要翻译：使用快速热氧化装置，浮栅电极的顶表面和侧表面被原位蒸汽发生（ISSG）氧化，其中加入约0.5％至33％氢的氧气直接引入具有温度约900至1100℃，压力为约1,000至2,000Pa，以便在加热的半导体衬底上从引入的氢气和氧气产生水蒸汽。因此，在浮栅电极的表面上形成由氧化硅制成的绝缘膜。

4. 发明授权

US06784040B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06784040B2
公开(公告)日：2004-08-31
申请号：US10382508
申请日：2003-03-07
申请人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
发明人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
摘要翻译：非易失性半导体存储器件具有沉积在控制栅电极的每个侧表面上的保护绝缘膜，以在形成浮栅电极期间保护控制栅电极，浮置栅极与其中一个侧表面相对控制栅电极，其间插入有保护绝缘膜，以便电容耦合到控制栅电极，形成在浮置栅电极和半导体衬底之间的隧道绝缘膜，形成在半导体衬底的包含并且形成在半导体衬底的与漏极区相对的控制栅电极相对的区域中的源极区。

5. 发明申请

US20120280328A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120280328A1
公开(公告)日：2012-11-08
申请号：US13554386
申请日：2012-07-20
申请人： Yoshiya MORIYAMA , Hiromasa FUJIMOTO , Satoru ITOU , Susumu AKAMATSU , Hiroshi OHKAWA
发明人： Yoshiya MORIYAMA , Hiromasa FUJIMOTO , Satoru ITOU , Susumu AKAMATSU , Hiroshi OHKAWA
IPC分类号： H01L27/092
CPC分类号： H01L29/7843 , H01L21/28123 , H01L21/28176 , H01L21/76895 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L23/485 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1
摘要翻译：半导体器件包括第一导电型第一MIS晶体管和第二导电型第二MIS晶体管。第一和第二MIS晶体管包括形成在由半导体衬底的分离区围绕的第一和第二有源区上的第一和第二栅极绝缘膜，以及形成在第一和第二栅极绝缘上的第一和第二栅电极电影。第一和第二栅极绝缘膜在分离区域的第一分离区域上彼此分离。在第一和第二有源区域的第一端之间的距离为第一和第二有源区域之间的距离，第一分隔区域彼此相对，并且从第一有源区域的第一端到第一栅极绝缘膜的第一端的突出量d1 在第一分离区域建立关系d1 <0.5s。

6. 发明申请

US20110163388A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110163388A1
公开(公告)日：2011-07-07
申请号：US13052546
申请日：2011-03-21
申请人： Kentaro NAKANISHI , Hiromasa Fujimoto , Takayuki Yamada
发明人： Kentaro NAKANISHI , Hiromasa Fujimoto , Takayuki Yamada
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.
摘要翻译：半导体器件包括n型MIS晶体管和p型MIS晶体管。 n型MIS晶体管包括形成在第一有源区上的第一栅电极和形成在第一栅电极的侧面上的第一侧壁。 p型MIS晶体管包括形成在第二有源区上的第二栅电极，形成在第二栅电极的侧面上的第二侧壁和形成在第二有源区中的应变层。第二侧壁具有比第一侧壁更小的厚度。

7. 发明授权

US07064375B2 Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof 失效
标题翻译：具有栅电极和扩散层的半导体存储器件及其制造方法
公开(公告)号：US07064375B2
公开(公告)日：2006-06-20
申请号：US10602595
申请日：2003-06-25
申请人： Keisuke Yonehama , Eiji Sakagami , Hiromasa Fujimoto , Naoki Koido
发明人： Keisuke Yonehama , Eiji Sakagami , Hiromasa Fujimoto , Naoki Koido
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A semiconductor memory device, including a first memory cell having a first gate electrode, a first diffusion layer, and a second diffusion layer; a first contact layer connected to the first diffusion layer of the first memory cell; a second contact layer connected to the first contact layer; a second memory cell having a second gate electrode, a third diffusion layer and a fourth diffusion layer, the second gate electrode of the second memory cell electrically connected to the first gate electrode of the first memory cell, the first and second memory cells arranged in a direction perpendicular to the first bit line; and a conductive layer commonly connected to the second diffusion layer of the first memory cell and the fourth diffusion layer of the second memory cell, a height of the conductive layer substantially being coplanar with a height of the first contact layer.
摘要翻译：一种半导体存储器件，包括具有第一栅电极，第一扩散层和第二扩散层的第一存储单元; 连接到第一存储单元的第一扩散层的第一接触层; 连接到所述第一接触层的第二接触层; 第二存储单元，具有第二栅电极，第三扩散层和第四扩散层，第二存储单元的第二栅电极与第一存储单元的第一栅极电连接，第一和第二存储单元布置在垂直于第一位线的方向; 以及与第一存储单元的第二扩散层和第二存储单元的第四扩散层共同连接的导电层，导电层的高度与第一接触层的高度基本上共面。

8. 发明申请

US20050161745A1 CMOS device, method for fabricating the same and method for generating mask data 审中-公开
标题翻译： CMOS器件，其制造方法以及用于生成掩模数据的方法
公开(公告)号：US20050161745A1
公开(公告)日：2005-07-28
申请号：US11028526
申请日：2005-01-05
申请人： Tokuhiko Tamaki , Hiromasa Fujimoto , Takatoshi Yasui , Takehiro Hirai
发明人： Tokuhiko Tamaki , Hiromasa Fujimoto , Takatoshi Yasui , Takehiro Hirai
IPC分类号： G03F1/20 , H01L21/266 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/76 , H01L31/062
CPC分类号： H01L21/823842
摘要： An NMIS gate implantation layer is generated by a method in which mask data of a P-type well implantation layer are added to mask data obtained by subtracting mask data of an NMIS-SD implantation layer and PMIS-SD implantation layer from mask data of an N-type well implantation layer. In a CMOS device fabricating process, ions are implanted into a polysilicon film by using the NMIS gate implantation layer, resulting in reduction in the total numbers of PN junctions and non-doped regions in a gate polysilicon film.
摘要翻译：通过将P型阱注入层的掩模数据添加到通过从掩模数据中减去NMIS-SD注入层和PMIS-SD注入层的掩模数据而获得的掩模数据的方法来产生NMIS栅极注入层 N型井注入层。在CMOS器件制造工艺中，通过使用NMIS栅极注入层将离子注入到多晶硅膜中，导致栅极多晶硅膜中PN结和非掺杂区域的总数减少。

9. 发明授权

US06828621B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
公开(公告)号：US06828621B2
公开(公告)日：2004-12-07
申请号：US10679431
申请日：2003-10-07
申请人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
发明人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

10. 发明授权

US06803623B2 Nonvolatile semiconductor memory device which can operate at high speed with low voltage, and manufacturing method there 失效
标题翻译：可以低电压高速运行的非易失性半导体存储器件，以及制造方法
公开(公告)号：US06803623B2
公开(公告)日：2004-10-12
申请号：US10003434
申请日：2001-12-06
申请人： Nobuyo Sugiyama , Shinji Odanaka , Hiromasa Fujimoto , Seiki Ogura
发明人： Nobuyo Sugiyama , Shinji Odanaka , Hiromasa Fujimoto , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： The nonvolatile semiconductor memory device has a floating gate electrode that is formed on the semiconductor region and stores carriers injected from the semiconductor region and a control gate electrode that controls the quantity of stored carriers by applying a predetermined voltage to the floating gate electrode. The source region is formed in the semiconductor region on one of side regions of the floating gate electrode and control gate electrode, while the drain region is formed on the other of the side regions thereof. The drain region creates an electric field from which the carriers injected into the floating gate electrode are subject to an external force having an element directed from the semiconductor region to the floating gate electrode.
摘要翻译：非易失性半导体存储器件具有形成在半导体区域上并存储从半导体区域注入的载流子的浮置栅电极和通过向浮置栅电极施加预定电压来控制存储载流量的控制栅电极。源极区域形成在浮置栅极电极和控制栅电极的一个侧区域的半导体区域中，而漏极区域形成在另一个侧面区域上。漏极区域产生电场，从该电场注入到浮栅中的载流子受到具有从半导体区域指向浮栅的元件的外力。

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