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1. 发明授权

US4704545A Switched capacitor rectifier circuit 失效
标题翻译：开关电容整流电路
公开(公告)号：US4704545A
公开(公告)日：1987-11-03
申请号：US751551
申请日：1985-07-03
申请人： Yutaka Tanaka , Hidemi Iseki
发明人： Yutaka Tanaka , Hidemi Iseki
IPC分类号： H02M7/21 , H02M7/217 , H03D1/00 , H03K5/22 , G06G7/18 , H03K5/153
CPC分类号： H02M7/2173
摘要： A rectifier circuit is disclosed in which the levels of an input signal and a reference signal are compared, and the polarity of the equivalent resistor is set at positive or negative depending on the result of the comparison. The equivalent resistor is connected, as an input resistor, to a differential amplifier. A feedback resistor is connected between the input and output of the differential amplifier. This arrangement enables the rectifier circuit, with only a single differential amplifier, to perform the rectifying operation with a gain.
摘要翻译：公开了一种整流电路，其中比较输入信号和参考信号的电平，并且根据比较结果将等效电阻的极性设置为正或负。等效电阻作为输入电阻连接到差分放大器。反馈电阻连接在差分放大器的输入和输出之间。这种布置使得仅具有单个差分放大器的整流器电路能够以增益执行整流操作。

2. 发明授权

US4599580A Circuit for comparing two or more frequencies 失效
标题翻译：用于比较两个或更多个频率的电路
公开(公告)号：US4599580A
公开(公告)日：1986-07-08
申请号：US672478
申请日：1984-11-16
申请人： Akira Yamaguchi , Hiroshi Shigehara , Hidemi Iseki
发明人： Akira Yamaguchi , Hiroshi Shigehara , Hidemi Iseki
IPC分类号： G01R23/00 , G10L19/02 , H03K3/0231 , H03K4/02 , H03L7/08
CPC分类号： H03K4/023 , G01R23/005 , G10L19/02 , H03K3/0231
摘要： According to a frequency comparing circuit of the present invention, there is provided a negative switched capacitor circuit having negative equivalent resistance, the value of which is determined according to the reference frequency and the frequency to be compared, and a positive switched capacitor circuit having positive equivalent resistance, the value of which is determined according to the reference frequency. A constant DC voltage is supplied in parallel to one terminal of the two switched capacitor circuits. The respective terminals of the switched capacitor circuits are commonly connected in order to produce the composite current of both output currents of the two switched capacitor circuits. The composite current is integrated by an integrator. Further, there is provided a Schmitt-type oscillating circuit. The oscillating frequency signal from the Schmitt-type oscillating circuit is supplied to the negative switched capacitor circuit. The higher level threshold voltage of the Schmitt-type oscillating circuit is determined according to the composite current of both output currents of the two switched capacitor circuits, thereby adjusting the frequency of the oscillating signal of the Schmitt-type oscillating circuit. The oscillating signal is supplied to the positive switched capacitor circuit. The lower level threshold voltage of the Schmitt-type oscillating circuit is determined according to the composite current of both output currents of the two switched capacitor circuits. Therefore, the frequency of the oscillating signal of the Schmitt-type oscillating circuit is adjusted.

3. 发明授权

US4741006A Up/down counter device with reduced number of discrete circuit elements 失效
标题翻译：具有减少数量的分立电路元件的上/下计数器件
公开(公告)号：US4741006A
公开(公告)日：1988-04-26
申请号：US754398
申请日：1985-07-12
申请人： Akira Yamaguchi , Koichi Satoh , Hidemi Iseki , Hiroshi Shigehara
发明人： Akira Yamaguchi , Koichi Satoh , Hidemi Iseki , Hiroshi Shigehara
IPC分类号： H03K23/56 , H03K23/00 , H03K23/04
CPC分类号： H03K23/56
摘要： An up/down counter device includes a D-type flip-flop circuit for producing a count signal of the 0th bit in synchronism with a clock signal, and 1st to n-th flip-flop circuits for producing count signals of the 1st to the n-th bits in synchronism with a clock signal. The first logic circuit is connected between the output of the D-type flip-flop circuit and the JK terminals of the first flip-flop circuit. The first stage logic circuit includes a first logic circuit section supplied with an up/down mode signal and the output signal of the D-type flip-flop circuit, and a second logic circuit connected in series with with the first logic circuit. Each of the 2nd to the n-th stage logic circuits includes a first logic circuit which is connected between the output terminal of the prestage flip-flop circuit and the JK terminals of the post stage flip-flop circuit, and a second logic circuit section connected to the first logic circuit. The output of the first logic circuit section of each of the first to the n-th logic circuits is connected to the input of the first logic circuit section of the post stage logic circuit.
摘要翻译：上/下计数器装置包括用于产生与时钟信号同步的第0位的计数信号的D型触发器电路，以及用于产生第1至第1位计数信号的第1至第n触发器电路第n位与时钟信号同步。第一逻辑电路连接在D型触发器电路的输出端与第一触发器电路的JK端子之间。第一级逻辑电路包括被提供有上/下模式信号和D型触发器电路的输出信号的第一逻辑电路部分和与第一逻辑电路串联连接的第二逻辑电路。第二至第n级逻辑电路中的每一个包括连接在前级触发器电路的输出端子和后级触发器电路的JK端子之间的第一逻辑电路，以及第二逻辑电路部分连接到第一逻辑电路。第一至第n逻辑电路中的每一个的第一逻辑电路部分的输出连接到后级逻辑电路的第一逻辑电路部分的输入端。

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