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1. 发明授权

US09543428B2 Silicon carbide semiconductor device and method for producing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US09543428B2
公开(公告)日：2017-01-10
申请号：US14400365
申请日：2013-06-06
申请人： DENSO CORPORATION , TOYOTA JIDOSHA KABUSHIKI KAISHA , Masahiro Sugimoto , Hidefumi Takaya , Akitaka Soeno , Jun Morimoto
发明人： Yuichi Takeuchi , Naohiro Suzuki , Masahiro Sugimoto , Hidefumi Takaya , Akitaka Soeno , Jun Morimoto , Narumasa Soejima , Yukihiko Watanabe
IPC分类号： H01L29/78 , H01L29/16 , H01L21/82 , H01L29/66 , H01L29/10 , H01L29/872 , H01L21/04 , H01L21/306 , H01L21/308 , H01L29/423 , H01L29/417 , H01L29/06 , H01L29/08 , H01L29/861
CPC分类号： H01L29/7811 , H01L21/046 , H01L21/0475 , H01L21/30604 , H01L21/308 , H01L21/761 , H01L21/8213 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/157 , H01L29/158 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/66068 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
摘要翻译： SiC半导体器件具有包含低浓度区域和填充在形成于单元区域的沟槽中的高浓度区域的p型区域。由低浓度区域提供p型列，并且由高浓度区域提供p +型深层。因此，由于可以通过由n型漂移层提供的p型列和n型列来形成SJ结构，所以可以降低导通电阻。由于漏极电位可以被p +型深层阻挡，所以在关断时，施加到栅极绝缘膜的电场可以减轻，从而可以限制栅极绝缘膜的破裂。因此，SiC半导体器件可以实现导通电阻的降低和栅极绝缘膜的破损的限制。

2. 发明申请

US20140097490A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140097490A1
公开(公告)日：2014-04-10
申请号：US14046361
申请日：2013-10-04
申请人： Hidefumi TAKAYA , Narumasa SOEJIMA
发明人： Hidefumi TAKAYA , Narumasa SOEJIMA
IPC分类号： H01L29/78
CPC分类号： H01L29/7831 , H01L29/0623 , H01L29/4236 , H01L29/42364 , H01L29/42368 , H01L29/66734 , H01L29/7813
摘要： A semiconductor substrate of a semiconductor device includes a body region of a first conductivity type, a drift region of a second conductivity type coming into contact with a lower surface of the body region, a gate electrode that is provided in a gate trench passing through the body region and extending to the drift region and faces the body region, and a gate insulator that is provided between the gate electrode and a wall surface of the gate trench. An inverted U-shaped section is formed in a lower surface of the gate insulator, and a floating region of the first conductivity type is formed in the inverted U-shaped section. The floating region protrudes under a portion that is located at a lowermost portion in the lower surface of the gate insulator.
摘要翻译：半导体器件的半导体衬底包括第一导电类型的主体区域，与主体区域的下表面接触的第二导电类型的漂移区域，设置在通过所述主体区域的栅极沟槽中的栅电极并且延伸到漂移区并面向身体区域，以及设置在栅极电极和栅极沟槽的壁表面之间的栅极绝缘体。在栅极绝缘体的下表面形成倒U字状的截面，在倒U字状的截面形成有第一导电型的浮动区域。浮动区域在位于栅极绝缘体的下表面中的最下部的部分下方突出。

3. 发明授权

US08525223B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US08525223B2
公开(公告)日：2013-09-03
申请号：US13450639
申请日：2012-04-19
申请人： Hiroki Watanabe , Shinichiro Miyahara , Masahiro Sugimoto , Hidefumi Takaya , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
发明人： Hiroki Watanabe , Shinichiro Miyahara , Masahiro Sugimoto , Hidefumi Takaya , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
IPC分类号： H01L21/02
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0634 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7397
摘要： A SiC semiconductor device includes: a SiC substrate including a first or second conductive type layer and a first conductive type drift layer and including a principal surface having an offset direction; a trench disposed on the drift layer and having a longitudinal direction; and a gate electrode disposed in the trench via a gate insulation film. A sidewall of the trench provides a channel formation surface. The vertical semiconductor device flows current along with the channel formation surface of the trench according to a gate voltage applied to the gate electrode. The offset direction of the SiC substrate is perpendicular to the longitudinal direction of the trench.
摘要翻译： SiC半导体器件包括：SiC衬底，包括第一或第二导电类型层和第一导电类型漂移层，并且包括具有偏移方向的主表面; 设置在所述漂移层上并具有纵向方向的沟槽; 以及通过栅极绝缘膜设置在沟槽中的栅电极。沟槽的侧壁提供通道形成表面。垂直半导体器件根据施加到栅电极的栅极电压与沟道形成表面一起流动电流。 SiC衬底的偏移方向垂直于沟槽的纵向方向。

4. 发明授权

US08334541B2 SiC semiconductor device 有权
标题翻译： SiC半导体器件
公开(公告)号：US08334541B2
公开(公告)日：2012-12-18
申请号：US13177747
申请日：2011-07-07
申请人： Shinichiro Miyahara , Hidefumi Takaya , Masahiro Sugimoto , Jun Morimoto , Yukihiko Watanabe
发明人： Shinichiro Miyahara , Hidefumi Takaya , Masahiro Sugimoto , Jun Morimoto , Yukihiko Watanabe
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7397 , H01L29/7828
摘要： A SiC semiconductor device includes a reverse type MOSFET having: a substrate; a drift layer and a base region on the substrate; a base contact layer and a source region on the base region; multiple trenches having a longitudinal direction in a first direction penetrating the source region and the base region; a gate electrode in each trench via a gate insulation film; an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed; a source electrode coupling with the source region and the base region through the contact hole; a drain electrode on the substrate. The source region and the base contact layer extend along with a second direction perpendicular to the first direction, and are alternately arranged along with the first direction. The contact hole has a longitudinal direction in the first direction.
摘要翻译： SiC半导体器件包括：反向型MOSFET，具有：衬底; 衬底上的漂移层和基极区域; 基极接触层和基极区上的源极区; 多个沟槽具有沿着第一方向的纵向方向穿过源极区域和基极区域; 通过栅极绝缘膜在每个沟槽中的栅电极; 覆盖所述栅电极且具有接触孔的层间绝缘膜，所述源极区域和所述基极接触层暴露在所述接触孔中; 源极通过接触孔与源极区域和基极区域耦合; 衬底上的漏电极。源区域和基底接触层与垂直于第一方向的第二方向一起延伸，并且与第一方向交替布置。接触孔沿第一方向具有纵向方向。

5. 发明申请

US20120187478A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120187478A1
公开(公告)日：2012-07-26
申请号：US13499599
申请日：2009-10-01
申请人： Hidefumi Takaya
发明人： Hidefumi Takaya
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0626 , H01L29/0878 , H01L29/4236 , H01L29/42368 , H01L29/66734 , H01L29/7808
摘要： Provided is a semiconductor device capable of suppressing deterioration in characteristics even when an Avalanche phenomenon occurs in the semiconductor device. The semiconductor device includes a first conductive type drift region; a second conductive type body region disposed on a front surface side of the drift region; a gate trench penetrating the body region and extending to the drift region; a gate electrode disposed within the gate trench; an insulator disposed between the gate electrode and a wall surface of the gate trench; and a second conductive type diffusion region surrounding a bottom portion of the gate trench. An impurity concentration and dimension of the diffusion region are adjusted such that a breakdown is to occur at a p-n junction between the diffusion region and the drift region when an Avalanche phenomenon is occurring.
摘要翻译：即使在半导体装置中发生雪崩现象的情况下，也能够抑制特性劣化的半导体装置。半导体器件包括第一导电型漂移区; 设置在所述漂移区域的前表面侧的第二导电型体区域; 穿过身体区域并延伸到漂移区域的栅极沟槽; 设置在所述栅极沟槽内的栅电极; 设置在所述栅极电极和所述栅极沟槽的壁表面之间的绝缘体; 以及围绕所述栅极沟槽的底部的第二导电型扩散区域。调整扩散区域的杂质浓度和尺寸，使得当发生雪崩现象时，在扩散区域和漂移区域之间的p-n结处发生击穿。

6. 发明申请

US20110291110A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20110291110A1
公开(公告)日：2011-12-01
申请号：US13117575
申请日：2011-05-27
申请人： Naohiro SUZUKI , Hideo MATSUKI , Masahiro SUGIMOTO , Hidefumi TAKAYA , Jun MORIMOTO , Tsuyoshi ISHIKAWA , Narumasa SOEJIMA , Yukihiko WATANABE
发明人： Naohiro SUZUKI , Hideo MATSUKI , Masahiro SUGIMOTO , Hidefumi TAKAYA , Jun MORIMOTO , Tsuyoshi ISHIKAWA , Narumasa SOEJIMA , Yukihiko WATANABE
IPC分类号： H01L29/12 , H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068
摘要： The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench.
摘要翻译：碳化硅半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极绝缘层，栅极电极，源极电极，漏极电极和深层。深层设置在基底区域下方并且位于比沟槽更深的深度。深层在与沟槽的纵向方向交叉的方向上分成多个部分。这些部分包括设置在与沟槽相对应的位置处的一组部分，其在沟槽的纵向方向上以相等的间隔布置。该组部分围绕沟槽的底部的角落。

7. 发明申请

US20110203513A1 METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE 审中-公开
标题翻译：制造碳化硅基板的方法
公开(公告)号：US20110203513A1
公开(公告)日：2011-08-25
申请号：US13029791
申请日：2011-02-17
申请人： Hiroki WATANABE , Yasuo Kitou , Kensaku Yamamoto , Hidefumi Takaya , Masahiro Sugimoto , Jun Morimoto , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
发明人： Hiroki WATANABE , Yasuo Kitou , Kensaku Yamamoto , Hidefumi Takaya , Masahiro Sugimoto , Jun Morimoto , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
IPC分类号： C30B19/12
CPC分类号： H01L21/02529 , C30B29/36 , C30B33/02 , H01L21/02378 , H01L21/02658 , H01L21/02667 , H01L29/66068
摘要： In a method of manufacturing a silicon carbide substrate, a defect-containing substrate made of silicon carbide is prepared. The defect-containing substrate has a front surface, a rear surface being opposite to the front surface, and a surface portion adjacent to the front surface. The detect-containing substrate includes a screw dislocation in the surface portion. The front surface of the defect-containing substrate is applied with an external force so that a crystallinity of the surface portion is reduced. After being applied with the external force, the defect-containing substrate is thermally treated so that the crystallinity of the surface portion is recovered.
摘要翻译：在制造碳化硅衬底的方法中，制备由碳化硅制成的含缺陷衬底。含缺陷的基板具有前表面，与前表面相对的后表面和与前表面相邻的表面部分。含检测基板包括在表面部分中的螺旋位错。使含有缺陷的基板的前表面被施加外力，使得表面部分的结晶度降低。在施加外力之后，对含缺陷的基板进行热处理，以恢复表面部分的结晶度。

8. 发明申请

US20170084735A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME 审中-公开
公开(公告)号：US20170084735A1
公开(公告)日：2017-03-23
申请号：US15365150
申请日：2016-11-30
申请人： Masahiro SUGIMOTO , Hidefumi TAKAYA , Akitaka SOENO , Jun MORIMOTO , DENSO CORPORATION , TOYOTA JIDOSHA KABUSHIKI KAISHA
发明人： Yuichi TAKEUCHI , Naohiro SUZUKI , Masahiro SUGIMOTO , Hidefumi TAKAYA , Akitaka SOENO , Jun MORIMOTO , Narumasa SOEJIMA , Yukihiko WATANABE
IPC分类号： H01L29/78 , H01L29/16 , H01L29/06 , H01L21/04 , H01L29/66 , H01L29/417 , H01L29/872 , H01L29/15 , H01L21/761
CPC分类号： H01L29/7811 , H01L21/046 , H01L21/0475 , H01L21/30604 , H01L21/308 , H01L21/761 , H01L21/8213 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/157 , H01L29/158 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/66068 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

9. 发明授权

US09136372B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US09136372B2
公开(公告)日：2015-09-15
申请号：US13531793
申请日：2012-06-25
申请人： Shinichiro Miyahara , Masahiro Sugimoto , Hidefumi Takaya , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
发明人： Shinichiro Miyahara , Masahiro Sugimoto , Hidefumi Takaya , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L29/04 , H01L29/08 , H01L29/10 , H01L29/16
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0865 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7825 , H01L29/7827
摘要： In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls.
摘要翻译：在碳化硅半导体器件中，多个沟槽在一个方向上具有纵向方向并且被布置成条纹图案。每个沟槽具有在纵向方向上延伸的第一和第二侧壁。第一侧壁与（11-20）面和（1-100）面中的一个成锐角，第二侧壁与（11-20）面和（1-100）平面，第一锐角小于第二锐角。第一导电类型区域仅与每个沟槽的第一和第二侧壁中的第一侧壁接触，并且仅在第一和第二侧壁中的第一侧壁上形成电流路径。

10. 发明授权

US09064952B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09064952B2
公开(公告)日：2015-06-23
申请号：US13042499
申请日：2011-03-08
申请人： Hidefumi Takaya
发明人： Hidefumi Takaya
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7811 , H01L29/0623 , H01L29/0653 , H01L29/0661 , H01L29/1095 , H01L29/7813
摘要： A semiconductor device 10 includes an element domain 40 and a termination domain 50 that surrounds the element domain 40. The element domain 40 and the termination domain 50 respectively include a second conductive type drift region 18. A gate trench 38 may be provided in the element domain 40. The termination domain 50 may be provided with a termination trench 22 surrounding the element domain. A first conductive type floating region surrounded by the drift region 18 is not provided at a bottom of the gate trench 38, and a first conductive type floating region 20 surrounded by the drift region 18 is provided at a bottom of the termination trench 22.
摘要翻译：半导体器件10包括元件结构域40和围绕元件区域40的端接区50.元件区域40和端接区域50分别包括第二导电型漂移区域18.栅极沟槽38可以设置在元件区域40中。终端域50可以设置有围绕元件域的终端沟槽22。由栅极沟槽38的底部没有设置由漂移区18包围的第一导电型浮置区域，并且在端接沟槽22的底部设置由漂移区18包围的第一导电型浮置区20。

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