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1. 发明授权

US10693466B2 Self-adaptive chip and configuration method 有权
公开(公告)号：US10693466B2
公开(公告)日：2020-06-23
申请号：US15748938
申请日：2015-07-31
申请人： Guosheng Wu , Qingdao Robei Electric Co., Ltd.
发明人： Guosheng Wu
IPC分类号： H03K19/17752 , G06F15/177 , G06F7/57 , H03K19/17728 , H03K19/17736 , G06F30/34
摘要： Disclosed are a self-adaptive chip (100) and configuration method. The self-adaptive chip includes: a plurality of dynamically reconfigurable cells arranged in an array, each of the plurality of dynamically reconfigurable cells being capable of being dynamically reconfigured as needed to execute different operating functions and/or input-output control functions, wherein, each of the plurality of dynamically reconfigurable cells is connected to multiple neighboring dynamically reconfigurable cells, to acquire data from one or more of the multiple neighboring dynamically reconfigurable cells, and output an operation result based on the data to at least one neighboring dynamically reconfigurable cell.

2. 发明申请

US20130053377A1 INHIBITORS OF BETA-SECRETASE 有权
标题翻译： BETA-SECRETASE的抑制剂
公开(公告)号：US20130053377A1
公开(公告)日：2013-02-28
申请号：US13575679
申请日：2011-02-23
申请人： Lawrence W. Dillard , Jing Yuan , Katerina Leftheris , Shankar Venkatraman , Guosheng Wu , Lanqi Jia , Zhenrong Xu , Salvacion Cacatian , Angel Morales-Ramos , Suresh Singh , Yajun Zheng
发明人： Lawrence W. Dillard , Jing Yuan , Katerina Leftheris , Shankar Venkatraman , Guosheng Wu , Lanqi Jia , Zhenrong Xu , Salvacion Cacatian , Angel Morales-Ramos , Suresh Singh , Yajun Zheng
IPC分类号： A61K31/5395 , C07D487/04 , A61K31/519 , C07D471/04 , A61K31/437 , C07D209/54 , A61K31/4035 , C07D401/10 , A61K31/4439 , C07D491/107 , C07D513/04 , A61K31/429 , A61P25/28 , A61P27/06 , C07D498/04
CPC分类号： C07D513/04 , C07D209/54 , C07D209/96 , C07D401/04 , C07D471/04 , C07D487/04 , C07D491/10 , C07D491/107 , C07D498/04
摘要： The present invention relates to compounds represented by Structural Formula (I) or a pharmaceutically acceptable salt thereof. Definitions for the variables are provided herein.
摘要翻译：本发明涉及由结构式（I）表示的化合物或其药学上可接受的盐。变量的定义在这里提供。

3. 发明申请

US20120133410A1 Clock Generation Circuit 失效
标题翻译：时钟发生电路
公开(公告)号：US20120133410A1
公开(公告)日：2012-05-31
申请号：US13215068
申请日：2011-08-22
申请人： Zhaolei Wu , Yalan Lv , Guosheng Wu
发明人： Zhaolei Wu , Yalan Lv , Guosheng Wu
IPC分类号： H03K3/01
CPC分类号： H03K4/501
摘要： A clock generation circuit, includes a first current source, a resistor connected to the first current source, a second current source, a first demux circuit connected to the second current source, a second demux circuit connected to the second current source, a capacitor connected to the first demux circuit and the second demux circuit, a first comparator connected to the first current source and the capacitor, a second comparator connected to the first current source and the capacitor, and a RS trigger connected both to the first comparator and the second comparator. The present invention has simple structure, small process variation, and lower cost, and is able to improve the accuracy of the clock with maximum possibility.
摘要翻译：时钟发生电路包括第一电流源，连接到第一电流源的电阻器，第二电流源，连接到第二电流源的第一解复用电路，连接到第二电流源的第二解复用电路，连接到第二电流源的电容器到第一解复用电路和第二解复用电路，连接到第一电流源和电容器的第一比较器，连接到第一电流源和电容器的第二比较器以及连接到第一比较器和第二比较器的第二比较器比较器。本发明结构简单，工艺变化小，成本低，能够以最大的可能性提高时钟的精度。

4. 发明申请

US20090010266A1 System of Extending Address on Atm Universal Test Operation Interface Bus and the Method Thereof 有权
标题翻译：在大气通用测试操作接口总线上扩展地址的系统及其方法
公开(公告)号：US20090010266A1
公开(公告)日：2009-01-08
申请号：US11664951
申请日：2005-09-09
申请人： ChangKong Yao , Guosheng Wu , Weifeng Shi
发明人： ChangKong Yao , Guosheng Wu , Weifeng Shi
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L43/50 , H04L2012/5628 , H04L2012/5685
摘要： The system of this invention for extending address on UTOPIA and the method thereof can extend the single PHY on the ATM switching chip bus to many PHY ports easily without increasing too much cost, and thus increase the application flexibility of corresponding ATM switching chips. Evidently, there would be still many other embodiments of the invention, the people skilled in the art can make a variety of corresponding changes and transformations in accordance with the invention without departing from its spirit and essential, but these corresponding changes and transformations should also be in the protection range of the claims of this invention.
摘要翻译：用于扩展UTOPIA上的地址的本发明的系统及其方法可以将ATM交换芯片总线上的单个PHY轻松扩展到多个PHY端口，而不会增加太多的成本，从而增加相应的ATM交换芯片的应用灵活性。显然，本发明还有许多其他实施例，本领域技术人员可以在不脱离其精神和基本要求的情况下，根据本发明进行各种相应的变化和变换，但是这些相应的变化和变化也应该是在本发明的权利要求的保护范围内。

5. 发明授权

US08804891B2 Frequency detector and method for detecting frequencies 有权
标题翻译：频率检测器和频率检测方法
公开(公告)号：US08804891B2
公开(公告)日：2014-08-12
申请号：US13215101
申请日：2011-08-22
申请人： Yong Quan , Guosheng Wu
发明人： Yong Quan , Guosheng Wu
IPC分类号： H03D3/24
CPC分类号： H04L7/0338
摘要： A frequency detector includes a multi-phase clock generation unit, a sampling unit connected to the multi-phase clock generation unit and a digital logic unit connected to the sampling unit. An inputted single-phase clock is received by the multi-phase clock generation unit and transformed into a multi-phase clock. Inputted random data are received by the sampling unit and sampled by the multi-phase clock. Each data bit of the random data is divided into several sampling intervals according to a phase number of the multi-phase clock. The digital logic unit analyzes sampling values logically, judges the corresponding sampling interval of each sampling value and outputs signals for indicating that a frequency of the random data is higher or lower than the frequency of the single-phase clock based on differences in the corresponding sampling intervals of the sampling values at two adjacent times. A method for detecting frequencies is further provided.
摘要翻译：频率检测器包括多相时钟生成单元，连接到多相时钟生成单元的采样单元和连接到采样单元的数字逻辑单元。输入的单相时钟由多相时钟发生单元接收并变换为多相时钟。输入的随机数据由采样单元接收并由多相时钟采样。随机数据的每个数据位根据多相时钟的相位数被分成几个采样间隔。数字逻辑单元逻辑地分析采样值，判定每个采样值的相应采样间隔，并输出用于指示随机数据的频率高于或低于单相时钟频率的信号，基于相应采样的差异在两个相邻时间的采样值的间隔。还提供一种检测频率的方法。

6. 发明授权

US08428115B2 Adaptive equalization system and method 有权
标题翻译：自适应均衡系统和方法
公开(公告)号：US08428115B2
公开(公告)日：2013-04-23
申请号：US13196152
申请日：2011-08-02
申请人： Ziche Zhang , Guosheng Wu
发明人： Ziche Zhang , Guosheng Wu
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04B3/145 , H04L25/03885
摘要： An adaptive equalization system includes an equalizer, a common-mode extraction buffer unit, a low-pass filter unit, a first and second energy compare units, a current comparator, and a digital control unit. The common-mode extraction buffer unit transmits a full spectral energy of an input signal received by the equalizer to the first energy compare unit and the low-pass filter unit, and extracts a common-mode signal of the input signal to the second energy compare unit. The first and second energy compare units respectively output a current signal characterized by the high-frequency energy and a current signal characterized by the low-frequency energy to the current comparator. Based on the compare result outputted by the current comparator, the digital control unit outputs an equalization control signal to the equalizer. The adaptive equalization system has the simple structure, and reduces the power consumption, the area and the manufacturing cost of the chip.
摘要翻译：自适应均衡系统包括均衡器，共模提取缓冲器单元，低通滤波器单元，第一和第二能量比较单元，电流比较器和数字控制单元。共模提取缓冲器单元将由均衡器接收的输入信号的全频谱能量发送到第一能量比较单元和低通滤波器单元，并将输入信号的共模信号提取到第二能量比较单元。第一和第二能量比较单元分别输出以高频能量为特征的电流信号和以电流比较器为特征的低频能量的电流信号。基于当前比较器输出的比较结果，数字控制单元向均衡器输出均衡控制信号。自适应均衡系统结构简单，降低了芯片的功耗，面积和制造成本。

7. 发明申请

US20120133395A1 High speed dynamic comparative latch 有权
公开(公告)号：US20120133395A1
公开(公告)日：2012-05-31
申请号：US12981514
申请日：2010-12-30
申请人： Bin Li , Guosheng Wu
发明人： Bin Li , Guosheng Wu
IPC分类号： H03K3/023
CPC分类号： H03K3/356173 , H03K5/249
摘要： A dynamic high-speed comparative latch comprises a pre-amplifier unit for enlarging input differential signals, a regenerating latch unit for latching outputted differential signals from the pre-amplifier unit by using a positive feedback, specifically, converting the output of the pre-amplifier unit into a latched result at a first state of a clock cycle, and then retaining the latched result and simultaneously resetting relevant nodes at a second state opposite to the first state of the clock cycle, and a latch unit for outputting the effective outputted value of the regenerating latch unit when the regenerating latch unit being in a retaining state. The pre-amplifier unit is connected with the regenerating latch unit, and the regenerating latch unit is connected with the latch unit. The pre-amplifier unit comprises only one input clock signal. The present invention has a simple structure, and ensures the correctness of the output result of the latch.

8. 发明申请

US20120072759A1 Timing Error Correction System and Method 审中-公开
标题翻译：定时纠错系统及方法
公开(公告)号：US20120072759A1
公开(公告)日：2012-03-22
申请号：US12939116
申请日：2010-11-03
申请人： Zhaolei Wu , Guosheng Wu
发明人： Zhaolei Wu , Guosheng Wu
IPC分类号： G06F1/12
CPC分类号： H03M9/00 , H04L7/0037 , H04L7/046
摘要： A timing error correction method used at the transmitting end in high-speed serial data transmission system comprises inputting a predefined parallel data training sequence and a clock signal, converting the training sequence into serial data, counting the number of the rising or falling edges of the serial data within a certain period, sending an adjustment signal for adjusting the time delay of the clock signal, obtaining a reasonable serialization timing, so that the number of the rising edges or falling edges of the serial data being equal to a predefined correct number. The corresponding timing error correction system comprises a data path, an adjustable delay clock path, a serialization unit for converting the parallel data into serial data, a driver unit, and a counting judging unit for counting the number of the rising or falling edges of the serial data and sending an adjustment signal to the adjustable delay clock path so as to control the timing of the serialization unit.
摘要翻译：在高速串行数据传输系统中在发送端使用的定时误差校正方法包括：输入预定义的并行数据训练序列和时钟信号，将训练序列转换成串行数据，对上述或下降沿的数量进行计数发送用于调整时钟信号的时间延迟的调整信号，获得合理的串行化定时，使得串行数据的上升沿或下降沿的数量等于预定义的正确数量。相应的定时误差校正系统包括数据通路，可调延迟时钟路径，用于将并行数据转换为串行数据的串行化单元，驱动器单元和计数判断单元，用于对上述或下降沿的数量进行计数串行数据，并将调整信号发送到可调延迟时钟路径，以便控制串行化单元的定时。

9. 发明申请

US20110299584A1 Equalization system 有权
标题翻译：均衡制度
公开(公告)号：US20110299584A1
公开(公告)日：2011-12-08
申请号：US13151754
申请日：2011-06-02
申请人： Zhaolei Wu , Guosheng Wu
发明人： Zhaolei Wu , Guosheng Wu
IPC分类号： H04L27/01
CPC分类号： H04B3/30 , H04L25/03057
摘要： An equalization system includes an adjustable equalization unit, a common-mode feedback unit connected with the equalization unit, a current balance driving unit connected with the feedback and equalization units, a first high-pass filter unit connected with the equalization unit, a second high-pass filter unit connected with the driving unit, a first low-pass filter unit connected with the equalization unit, a second low-pass filter unit connected with the driving unit, a first energy detection unit connected with two high-pass filter units, a second energy detection unit connected with two low-pass filter units, a first analog-to-digital converter unit connected with the first energy detection unit, a second analog-to-digital converter unit connected with the second energy detection unit and a state decision unit connected with two analog-to-digital converter units outputs a control signal for adjusting the equalization unit. It improves the signal quality of the receiver of the high-speed signal transmission system.
摘要翻译：均衡系统包括可调均衡单元，与均衡单元连接的共模反馈单元，与反馈和均衡单元连接的电流平衡驱动单元，与均衡单元连接的第一高通滤波器单元，第二高与所述驱动单元连接的第一低通滤波器单元，与所述均衡单元连接的第一低通滤波器单元，与所述驱动单元连接的第二低通滤波器单元，与两个高通滤波器单元连接的第一能量检测单元，与两个低通滤波器单元连接的第二能量检测单元，与第一能量检测单元连接的第一模数转换器单元，与第二能量检测单元连接的第二模数转换单元和状态与两个模拟 - 数字转换器单元连接的判定单元输出用于调整均衡单元的控制信号。它提高了高速信号传输系统接收机的信号质量。

10. 发明授权

US08067967B2 Phase delay line 有权
标题翻译：相位延迟线
公开(公告)号：US08067967B2
公开(公告)日：2011-11-29
申请号：US12501386
申请日：2009-07-10
申请人： Ziche Zhang , Guosheng Wu
发明人： Ziche Zhang , Guosheng Wu
IPC分类号： H03L7/06
CPC分类号： H03L7/099 , H03K5/13 , H03K5/15066 , H03K5/15073 , H03K5/1565 , H03K2005/00052 , H03L7/0891
摘要： A phase delay line comprises a phase-locked loop, a duty-cycle adjusting ring and a voltage-sharing to time-sharing converter, wherein the phase-locked loop and the duty-cycle adjusting ring form a loop, and one output of the phase-locked loop is connected with the input of the voltage-sharing to time-sharing converter. The voltage can be precisely divided, and the number of the phases can be easily controlled and expanded. The band gap reference technology enables the working points not affected by the temperature. The negative feedback mechanism of the phase-locked loop determines the period, phase, duty-cycle of the sawtooth wave are same with the reference clock. The ascending and descending time of the sawtooth wave are precisely equal.
摘要翻译：相位延迟线包括锁相环，占空比调节环和对共享转换器的电压共享，其中锁相环和占空比调节环形成环路，并且一个输出端锁相环与分压转换器的分压输入相连。可以精确地划分电压，并且可以容易地控制和扩展相的数量。带隙参考技术使工作点不受温度影响。锁相环的负反馈机制决定了锯齿波的周期，相位，占空比与参考时钟相同。锯齿波的上升和下降时间是相当的。

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