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1. 发明申请

US20070044059A1 IP placement validation 失效
标题翻译： IP位置验证
公开(公告)号：US20070044059A1
公开(公告)日：2007-02-22
申请号：US11204670
申请日：2005-08-16
申请人： Gregor Martin , Ying He , Grant Lindberg
发明人： Gregor Martin , Ying He , Grant Lindberg
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for defining valid placement of intellectual property (IP) blocks within a platform application specific integrated circuit comprising the steps of (A) extracting IP recorded information for an intellectual property (IP) block to be placed on a platform application specific integrated circuit, (B) extracting device data for the platform application specific integrated circuit and (C) determining one or more valid placement locations for the intellectual property (IP) block based upon the IP recorded information and the device data.
摘要翻译：一种用于在平台专用集成电路内定义知识产权（IP）块的有效放置的方法，包括以下步骤：（A）提取要放置在平台应用专用集成电路上的知识产权（IP）块的IP记录信息，（B）提取用于平台应用专用集成电路的设备数据;（C）基于IP记录信息和设备数据确定知识产权（IP）块的一个或多个有效位置位置。

2. 发明申请

US20070044058A1 Enabling efficient design reuse in platform ASICs 有权
公开(公告)号：US20070044058A1
公开(公告)日：2007-02-22
申请号：US11204669
申请日：2005-08-16
申请人： Ying He , Gregor Martin , Grant Lindberg
发明人： Ying He , Gregor Martin , Grant Lindberg
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A design tool for generating design views of a semiconductor chip is presented. The design tool includes an input module, a generation module, a first synthesis module, a user interface module and an extraction module. The input module may be configured to receive input including physical and logical resources and a custom chip specification. The generation module may be configured to generate Register Transfer Level (RTL) views for the semiconductor chip. The first synthesis module may be configured to perform logic synthesis using the RTL views. The user interface module may be configured to query a user whether re-usable intellectual property (IP) is to be generated. The extraction module may be configured to extract and package design information for the re-usable IP in response to a request from the user.

3. 发明申请

US20070028196A1 Resource estimation for design planning 失效
标题翻译：设计规划资源估算
公开(公告)号：US20070028196A1
公开(公告)日：2007-02-01
申请号：US11194299
申请日：2005-08-01
申请人： Gregor Martin , Grant Lindberg , Ying He
发明人： Gregor Martin , Grant Lindberg , Ying He
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for estimating resources during design planning is generally provided. A first step generally involves receiving design information for an integrated circuit design. A first portion of the integrated circuit design is generally complete, while a second portion of the integrated circuit design is generally incomplete. A second step generally involves receiving user input of estimated design information for the second portion of the integrated circuit design. A third step generally involves automatically generating one or more representative blocks representing the second portion of the integrated circuit design based on the user input. The one or more representative blocks may be generated having substantially equivalent size and characteristics to one or more actual blocks developed for the second portion of the integrated circuit design.
摘要翻译：通常提供在设计规划期间估计资源的方法。第一步通常涉及接收集成电路设计的设计信息。集成电路设计的第一部分通常是完整的，而集成电路设计的第二部分通常是不完整的。第二步通常涉及接收用于集成电路设计的第二部分的估计设计信息的用户输入。第三步通常涉及基于用户输入自动产生代表集成电路设计的第二部分的一个或多个代表性块。可以生成一个或多个代表性块，其具有与针对集成电路设计的第二部分开发的一个或多个实际块基本上相同的大小和特性。

4. 发明申请

US20060129963A1 Floorplan visualization method 有权
标题翻译：平面图可视化方法
公开(公告)号：US20060129963A1
公开(公告)日：2006-06-15
申请号：US11012741
申请日：2004-12-15
申请人： Gregor Martin , Ying He , Grant Lindberg
发明人： Gregor Martin , Ying He , Grant Lindberg
IPC分类号： G06F9/455 , G06F9/45 , G06F17/50
CPC分类号： G06F17/5072
摘要： A method for floorplan visualization comprising the steps of (A) receiving design information for an integrated circuit design comprising one or more subsystems, (B) generating one or more gate count estimates for the one or more subsystems of the integrated circuit design, (C) generating one or more gate density estimates for gates of the one or more subsystems mapped to one or more programmable areas of a programmable platform device and (D) generating a visual representation of one or more area estimations for each of the one or more subsystems based on the one or more gate count estimates and the one or more gate density estimates.
摘要翻译：一种用于平面图可视化的方法，包括以下步骤：（A）接收包括一个或多个子系统的集成电路设计的设计信息，（B）为集成电路设计的一个或多个子系统生成一个或多个门计数估计，（C ）生成映射到可编程平台设备的一个或多个可编程区域的一个或多个子系统的门的一个或多个门密度估计，以及（D）生成针对所述一个或多个子系统中的每一个的一个或多个区域估计的视觉表示基于一个或多个门计数估计和一个或多个门密度估计。

5. 发明授权

US08099708B2 I/O planning with lock and insertion features 有权
标题翻译：具有锁定和插入功能的I / O规划
公开(公告)号：US08099708B2
公开(公告)日：2012-01-17
申请号：US12432996
申请日：2009-04-30
申请人： Grant Lindberg , Gregor J. Martin , David Asson , Ying Chun He
发明人： Grant Lindberg , Gregor J. Martin , David Asson , Ying Chun He
IPC分类号： G06F17/50 , G06F15/04
CPC分类号： G06F17/5072
摘要： A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.
摘要翻译：公开了一种用于输入/输出分配工具的操作方法。该方法通常包括以下步骤：（A）向用户生成图形呈现，显示（i）具有多个针图标的电路图标和（ii）多个信号图标，（B）移动第一信号图标响应于来自用户的移动命令，在图形呈现中到第一个针图标，以及（C）响应于通过规则的关联来指示接受第一信号图标和第一针图标之间的关联。

6. 发明申请

US20090210846A1 I/O PLANNING WITH LOCK AND INSERTION FEATURES 有权
标题翻译：具有锁定和插入功能的I / O计划
公开(公告)号：US20090210846A1
公开(公告)日：2009-08-20
申请号：US12432996
申请日：2009-04-30
申请人： Grant Lindberg , Gregor J. Martin , David Asson , Ying Chun He
发明人： Grant Lindberg , Gregor J. Martin , David Asson , Ying Chun He
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.
摘要翻译：公开了一种用于输入/输出分配工具的操作方法。该方法通常包括以下步骤：（A）向用户生成图形呈现，显示（i）具有多个针图标的电路图标和（ii）多个信号图标，（B）移动第一信号图标响应于来自用户的移动命令，在图形呈现中到第一个针图标，以及（C）响应于通过规则的关联来指示接受第一信号图标和第一针图标之间的关联。

7. 发明授权

US07543261B2 I/O planning with lock and insertion features 失效
标题翻译：具有锁定和插入功能的I / O规划
公开(公告)号：US07543261B2
公开(公告)日：2009-06-02
申请号：US11115798
申请日：2005-04-27
申请人： Grant Lindberg , Gregor J. Martin , David Asson , Ying Chun He
发明人： Grant Lindberg , Gregor J. Martin , David Asson , Ying Chun He
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072
摘要： A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.
摘要翻译：公开了一种用于输入/输出分配工具的操作方法。该方法通常包括以下步骤：（A）向用户生成图形呈现，显示（i）具有多个针图标的电路图标和（ii）多个信号图标，（B）移动第一信号图标响应于来自用户的移动命令，在图形呈现中到第一个针图标，以及（C）响应于通过规则的关联来指示接受第一信号图标和第一针图标之间的关联。

8. 发明授权

US07464345B2 Resource estimation for design planning 失效
标题翻译：设计规划资源估算
公开(公告)号：US07464345B2
公开(公告)日：2008-12-09
申请号：US11194299
申请日：2005-08-01
申请人： Gregor J. Martin , Grant Lindberg , Ying Chun He
发明人： Gregor J. Martin , Grant Lindberg , Ying Chun He
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for estimating resources during design planning is generally provided. A first step generally involves receiving design information for an integrated circuit design. A first portion of the integrated circuit design is generally complete, while a second portion of the integrated circuit design is generally incomplete. A second step generally involves receiving user input of estimated design information for the second portion of the integrated circuit design. A third step generally involves automatically generating one or more representative blocks representing the second portion of the integrated circuit design based on the user input. The one or more representative blocks may be generated having substantially equivalent size and characteristics to one or more actual blocks developed for the second portion of the integrated circuit design.
摘要翻译：通常提供在设计规划期间估计资源的方法。第一步通常涉及接收集成电路设计的设计信息。集成电路设计的第一部分通常是完整的，而集成电路设计的第二部分通常是不完整的。第二步通常涉及接收用于集成电路设计的第二部分的估计设计信息的用户输入。第三步通常涉及基于用户输入自动产生代表集成电路设计的第二部分的一个或多个代表性块。可以生成一个或多个代表性块，其具有与针对集成电路设计的第二部分开发的一个或多个实际块基本上相同的大小和特性。

9. 发明授权

US07290224B2 Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit 失效
标题翻译：引导捕获，创建和无缝集成，将时钟规范的可扩展复杂度集成到集成电路的设计流程中
公开(公告)号：US07290224B2
公开(公告)日：2007-10-30
申请号：US11027266
申请日：2004-12-31
申请人： Jonathan Byrn , Grant Lindberg
发明人： Jonathan Byrn , Grant Lindberg
IPC分类号： G06F17/50
CPC分类号： G06F1/04 , G06F9/453
摘要： A method and tool that capture, create, and integrate a clock specification to achieve a correct-by-construction design flow of a semiconductor product from a partially manufactured semiconductor platform. The clocking elements of the design flow are combined and displayed in a plurality of context-driven views. Within each view, details of the clock specification are presented in the context of the information. A user may zoom in/out through the plurality of views of the design flow for more or less detailed information. Each view can combine the logical, structural, architectural, cost, timing, and other features of the clock in a particular context. A user can zoom in to select and manipulate circuit elements. The user can then zoom out and the present invention determines how changes affect other clocks in the same or other modules and/or the same clock in other modules.
摘要翻译：捕获，创建和集成时钟规范以实现部分制造的半导体平台的半导体产品的正确的设计流程的方法和工具。设计流程的时钟元素被组合并显示在多个上下文驱动视图中。在每个视图中，时钟规范的细节在信息的上下文中呈现。用户可以通过设计流程的多个视图来放大/缩小或多或少的详细信息。每个视图可以在特定的上下文中组合时钟的逻辑，结构，架构，成本，时间和其他特征。用户可以放大以选择和操纵电路元件。然后，用户可以缩小并且本发明确定变化如何影响其他模块中相同或其他模块和/或相同时钟中的其他时钟。

10. 发明申请

US20060248491A1 I /O planning with lock and insertion features 失效
标题翻译：具有锁定和插入功能的I / O规划
公开(公告)号：US20060248491A1
公开(公告)日：2006-11-02
申请号：US11115798
申请日：2005-04-27
申请人： Grant Lindberg , Gregor Martin , David Asson , Ying He
发明人： Grant Lindberg , Gregor Martin , David Asson , Ying He
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5072
摘要： A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.
摘要翻译：公开了一种用于输入/输出分配工具的操作方法。该方法通常包括以下步骤：（A）向用户生成图形呈现，显示（i）具有多个针图标的电路图标和（ii）多个信号图标，（B）移动第一信号图标响应于来自用户的移动命令，在图形呈现中到第一个针图标，以及（C）响应于通过规则的关联来指示接受第一信号图标和第一针图标之间的关联。

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