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1. 再颁专利

USRE43541E1 Control circuitry for a non-volatile memory 有权
标题翻译：用于非易失性存储器的控制电路
公开(公告)号：USRE43541E1
公开(公告)日：2012-07-24
申请号：US11588332
申请日：2006-10-25
申请人： Glen Arnold Rosendale
发明人： Glen Arnold Rosendale
IPC分类号： G11C16/04
CPC分类号： G11C7/106 , G11C7/1051 , G11C8/08 , G11C16/12
摘要： Control circuitry for applying voltages to a memory circuit. In accordance with this invention, row Row circuitry applies either a high voltage or a low voltage to a memory cell based on the operation to be performed and column circuitry applies a high or a low voltage to the memory cell based on the operation to be performed.
摘要翻译：用于向存储器电路施加电压的控制电路。根据本发明，行行电路基于要执行的操作将高电压或低电压施加到存储器单元，并且基于要执行的操作向存储器单元施加高电压或低电压的列电路。

2. 发明申请

US20110216572A1 ELECTRICALLY PROGRAMMABLE FUSE BIT 审中-公开
标题翻译：电子可编程保险丝位
公开(公告)号：US20110216572A1
公开(公告)日：2011-09-08
申请号：US13024231
申请日：2011-02-09
申请人： Jack Zezhong Peng , David Fong , Glen Arnold Rosendale
发明人： Jack Zezhong Peng , David Fong , Glen Arnold Rosendale
IPC分类号： G11C17/16
CPC分类号： G11C17/18
摘要： One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.
摘要翻译：公开了一次性可编程（OTP）非易失性熔丝存储器单元，其不需要用于读取其数据内容的解码或寻址。每个保险丝存储单元的内容在其输出端被锁存并且始终可用，并且可以用于例如代码存储存储器，串行配置存储器，以及作为用于ID（识别），修整和其他后期处理的单个保险丝位。制造片上系统（SoC）定制需求。还提供了用于设计测试等的临时数据存储的手段。在替代实施例中，在单个存储器单元中使用两个差分编程的熔丝，合并选择和编程电路。

3. 发明授权

US06809965B2 Control circuitry for a non-volatile memory 有权
标题翻译：用于非易失性存储器的控制电路
公开(公告)号：US06809965B2
公开(公告)日：2004-10-26
申请号：US10247767
申请日：2002-09-18
申请人： Glen Arnold Rosendale
发明人： Glen Arnold Rosendale
IPC分类号： G11C1604
CPC分类号： G11C7/106 , G11C7/1051 , G11C8/08 , G11C16/12
摘要： Control circuitry for applying voltages to a memory circuit. In accordance with this invention, row circuitry applies either a high voltage or a low voltage to a memory cell based on the operation to be performed and column circuitry applies a high or a low voltage to the memory cell based on the operation to be performed.
摘要翻译：用于向存储器电路施加电压的控制电路。根据本发明，基于要执行的操作，行电路将高电压或低电压施加到存储器单元，并且列电路基于要执行的操作向存储器单元施加高电压或低电压。

4. 发明授权

US07609539B2 Electrically programmable fuse bit 有权
标题翻译：电可编程熔丝位
公开(公告)号：US07609539B2
公开(公告)日：2009-10-27
申请号：US11699916
申请日：2007-01-29
申请人： Jack Zezhong Peng , David Fong , Glen Arnold Rosendale
发明人： Jack Zezhong Peng , David Fong , Glen Arnold Rosendale
IPC分类号： G11C17/00 , G11C17/18
CPC分类号： G11C17/18
摘要： One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs.
摘要翻译：公开了一次性可编程（OTP）非易失性熔丝存储器单元，其不需要用于读取其数据内容的解码或寻址。每个保险丝存储单元的内容在其输出端被锁存并且始终可用，并且可以用于例如代码存储存储器，串行配置存储器，以及作为用于ID（识别），修整和其他后期处理的单个保险丝位。制造片上系统（SoC）定制需求。

5. 发明授权

US07173851B1 3.5 transistor non-volatile memory cell using gate breakdown phenomena 有权
标题翻译： 3.5晶体管非易失性存储单元采用栅极击穿现象
公开(公告)号：US07173851B1
公开(公告)日：2007-02-06
申请号：US11252461
申请日：2005-10-18
申请人： John M. Callahan , Hemanshu T. Vernenker , Michael D. Fliesler , Glen Arnold Rosendale , Harry Shengwen Luan , Zhongshang Liu
发明人： John M. Callahan , Hemanshu T. Vernenker , Michael D. Fliesler , Glen Arnold Rosendale , Harry Shengwen Luan , Zhongshang Liu
IPC分类号： G11C11/34
CPC分类号： G11C17/18 , G11C17/16
摘要： A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.
摘要翻译：形成在具有列位线和行字线的存储器阵列中有用的可编程存储器单元。存储单元包括其栅极连接到程序字线的击穿晶体管和在感测节点处串联连接到所述击穿晶体管的写入晶体管。写晶体管的栅极连接到写字线。此外，第一感测晶体管的栅极连接到感测节点。第二感测晶体管与第一感测晶体管串联连接，并且其栅极连接到读字线。第二感测晶体管的源极连接到列位线。

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