会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20090001381A1
    • 2009-01-01
    • US12153953
    • 2008-05-28
    • Toshiharu MaruiHideyuki OkitaShinichi HoshiFumihiko Toda
    • Toshiharu MaruiHideyuki OkitaShinichi HoshiFumihiko Toda
    • H01L29/778
    • H01L29/0653H01L29/2003H01L29/66462H01L29/7787
    • A semiconductor device includes a substrate, laminated layers provided on the substrate. The laminated layers include an AlGaN barrier layer as an uppermost layer. A gate electrode is provided in a channel region of the laminated layers. A source electrode and a drain electrode are provided so as to face each other via the channel region interposed therebetween. A silicon nitride film is formed to cover an exposed surface of the laminated layers exposed via the gate electrode, the source electrode and the drain electrode. The silicon nitride film has characteristics that an etching rate thereof is in a range from 1 nm per/min to 2 nm/min for an etchant in which hydrofluoric acid having a concentration of 50 weight percent and ammonium fluoride having a concentration of 40 weight percent are mixed at a mixing ratio of 1:9.
    • 半导体器件包括衬底,设置在衬底上的层叠层。 层叠层包括作为最上层的AlGaN阻挡层。 栅电极设置在层叠层的沟道区域中。 源电极和漏电极经由插入其间的沟道区域彼此面对地设置。 形成氮化硅膜以覆盖经由栅电极,源电极和漏电极露出的层叠层的暴露表面。 氮化硅膜的特征在于,对于浓度为50重量%的氢氟酸和浓度为40重量%的氟化铵的蚀刻剂,其蚀刻速率在1nm / min〜2nm / min的范围内 以1:9的混合比混合。
    • 5. 发明申请
    • Method for fabricating AIGaN/GaN-HEMT using selective regrowth
    • 使用选择性再生长制造AIGaN / GaN-HEMT的方法
    • US20080176366A1
    • 2008-07-24
    • US11984015
    • 2007-11-13
    • Juro MitaFumihiko TodaToshiharu Marui
    • Juro MitaFumihiko TodaToshiharu Marui
    • H01L21/338
    • H01L29/7786H01L29/2003H01L29/42316H01L29/66462
    • A semiconductor body includes, on a substrate, a stack of buffer layer, UID-GaN layer overlying the buffer layer, and UID-AlGaN layer overlying the UID-GaN layer. On the surface of the UID-AlGaN layer, an insulation film is deposited and patterned. An n+-GaN layer is selectively regrown directly on a region of the surface of the semiconductor body other than the insulation film using the patterned insulation film as a mask without etching the surface of the semiconductor body. A portion of the selectively regrown n+-GaN layer corresponding to a region reserved for an ohmic contact electrode is defined and the ohmic contact electrode is formed on the region. An opening exposing a region reserved for a gate electrode is defined and formed within the insulation SiO2 layer, and a gate electrode is formed in the region. An AlGaN/GaN-HEMT or MIS type of AlGaN/GaN-HEMT has lower contact resistance and uniform device characteristics.
    • 半导体本体在衬底上包括一叠缓冲层,覆盖缓冲层的UID-GaN层和覆盖在UID-GaN层上的UID-AlGaN层。 在UID-AlGaN层的表面上,淀积并图案化绝缘膜。 在不蚀刻半导体本体的表面的情况下,使用图案化的绝缘膜作为掩模,在半导体本体的除了绝缘膜之外的区域的区域上选择性地重新生长n + SUP / GaN。 限定与欧姆接触电极保留的区域对应的部分选择性再生长的n + S + GaN层,并且在该区域上形成欧姆接触电极。 在绝缘SiO 2层内限定并形成露出用于栅电极的区域的开口,并且在该区域中形成栅电极。 AlGaN / GaN-HEMT或MIS型AlGaN / GaN-HEMT具有较低的接触电阻和均匀的器件特性。
    • 7. 发明授权
    • Semiconductor device and manufacturing method
    • 半导体器件及制造方法
    • US07763910B2
    • 2010-07-27
    • US12382664
    • 2009-03-20
    • Toshiharu MaruiFumihiko TodaShinichi Hoshi
    • Toshiharu MaruiFumihiko TodaShinichi Hoshi
    • H01L29/778
    • H01L29/7786H01L29/402H01L29/42316H01L29/66462
    • A semiconductor device has source and drain electrodes formed on a substrate, a gate insulation film formed on the substrate between the source and drain electrodes, and a gate electrode formed on the gate insulation film. These elements are all covered by a dielectric sub-insulation film. An opening is formed in the sub-insulation film, partially exposing the gate electrode. A field plate extends from the top of the gate electrode down one side of the gate electrode as far as the sub-insulation film covering the gate insulation film, filling the opening. The thickness of the sub-insulation film can be selected to optimize the separation between the field plate and the substrate for the purpose of reducing current collapse by reducing electric field concentration at the edge of the gate electrode.
    • 半导体器件具有形成在基板上的源极和漏极,在源极和漏极之间的基板上形成的栅极绝缘膜,以及形成在栅极绝缘膜上的栅电极。 这些元件都被绝缘子绝缘膜覆盖。 在副绝缘膜中形成开口,部分地露出栅电极。 场板从栅电极的顶部向下延伸到栅电极的一侧,直到覆盖栅绝缘膜的次绝缘膜填充开口。 可以选择次级绝缘膜的厚度以优化场板和衬底之间的分离,以便通过降低栅电极边缘处的电场浓度来减少电流崩塌。
    • 8. 发明申请
    • Semiconductor device and manufacturing method
    • 半导体器件及制造方法
    • US20090242937A1
    • 2009-10-01
    • US12382664
    • 2009-03-20
    • Toshiharu MaruiFumihiko TodaShinichi Hoshi
    • Toshiharu MaruiFumihiko TodaShinichi Hoshi
    • H01L29/778H01L21/336
    • H01L29/7786H01L29/402H01L29/42316H01L29/66462
    • A semiconductor device has source and drain electrodes formed on a substrate, a gate insulation film formed on the substrate between the source and drain electrodes, and a gate electrode formed on the gate insulation film. These elements are all covered by a dielectric sub-insulation film. An opening is formed in the sub-insulation film, partially exposing the gate electrode. A field plate extends from the top of the gate electrode down one side of the gate electrode as far as the sub-insulation film covering the gate insulation film, filling the opening. The thickness of the sub-insulation film can be selected to optimize the separation between the field plate and the substrate for the purpose of reducing current collapse by reducing electric field concentration at the edge of the gate electrode.
    • 半导体器件具有形成在基板上的源极和漏极,在源极和漏极之间的基板上形成的栅极绝缘膜,以及形成在栅极绝缘膜上的栅电极。 这些元件都被绝缘子绝缘膜覆盖。 在副绝缘膜中形成开口,部分地露出栅电极。 场板从栅电极的顶部向下延伸到栅电极的一侧,直到覆盖栅绝缘膜的次绝缘膜填充开口。 可以选择次级绝缘膜的厚度以优化场板和衬底之间的分离,以便通过降低栅电极边缘处的电场浓度来减少电流崩塌。